CY7C1421AV18-278BZI datasheet, PDF

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CY7C1421AV18-278BZI: DescriptionDDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165; Categorystorage storage; File Size468KB，28 Pages; ManufacturerCypress Semiconductor

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CY7C1421AV18-278BZI Overview

DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

CY7C1421AV18-278BZI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	278 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.26 A
Minimum standby current	1.7 V
Maximum slew rate	0.775 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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CY7C1417AV18

CY7C1428AV18

CY7C1419AV18

CY7C1421AV18

36-Mbit DDR-II SRAM 4-Word Burst

Architecture

Features

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

• 300-MHz clock for high bandwidth

• 4-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V

)

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Functional Description

The CY7C1417AV18, CY7C1428AV18, CY7C1419AV18 and

CY7C1421AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II (Double Data Rate) architecture. The

DDR-II consists of an SRAM core with advanced synchronous

peripheral circuitry and a two-bit burst counter. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with four 8-bit

words in the case of CY7C1417AV18 and four 9-bit words in

the case of CY7C1428AV18 that burst sequentially into or out

of the device. The burst counter always starts with “00” inter-

nally in the case of CY7C1417AV18 and CY7C1428AV18. On

CY7C1419AV18 and CY7C1421AV18, the burst counter takes

in the last two significant bits of the external address and

bursts four 18-bit words in the case of CY7C1419AV18, and

four 36-bit words in the case of CY7C1421AV18, sequentially

into or out of the device.

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SRAM

in the system design. Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Configurations

CY7C1417AV18 – 4M x 8

CY7C1428AV18 – 4M x 9

CY7C1419AV18 – 2M x 18

CY7C1421AV18 – 1M x 36

Selection Guide

300 MHz

Maximum Operating Frequency

Maximum Operating Current

300

825

278 MHz

278

775

250 MHz

250

700

200 MHz

200

600

167 MHz

167

500

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 38-05618 Rev. *E

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised September 25, 2006

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