DS1007-9 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> DS1007-9

DS1007-9: DescriptionSilicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16; Categorylogic logic; File Size55KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Related ProductsFound13parts with similar functions to DS1007-9

Download Datasheet Parametric Compare View All

DS1007-9 Overview

Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16

DS1007-9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	DIP
package instruction	0.300 INCH, DIP-16
Contacts	16
Reach Compliance Code	not_compliant
series	1007
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.175 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	1
Number of functions	7
Number of taps/steps	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Maximum supply current (ICC)	70 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	35 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
Total delay nominal (td)	35 ns
width	7.62 mm

Preview

Download Datasheet

View All

DS1007

7-1 Silicon Delay Line

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

All-silicon time delay

IN1

IN3

7 independent buffered delays

OUT1

OUT3

Delay tolerance ±2 ns

Four delays can be custom set between 3 ns

IN4

IN2

IN3

IN1

and 10 ns

OUT2

OUT4

OUT3

OUT1

Three delays can be custom set between 9 ns

IN4

IN2

GND

and 40 ns

OUT4

OUT2

OUT7

IN5

GND

Delays are stable and precise

OUT7

IN5

OUT5

Economical

IN7

OUT5

Auto-insertable, low profile

IN6

OUT6

IN6

OUT6

Surface mount 16-pin SOIC

DS1007 16-Pin DIP (300-mil)

DS1007S 16-Pin SOIC

Low-power CMOS

See Mech. Drawings Section

(300-mil)

TTL/CMOS-compatible

See Mech. Drawings Section

Vapor phase, IR and wave solderable

Custom specifications available

PIN DESCRIPTION

Quick turn prototypes

IN1 - IN7

- Inputs

Out1 – Out7 - Outputs

GND

- Ground

- +5 Volts

DESCRIPTION

The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas

Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an

accuracy of

±2

ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.

Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to

older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after

the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special

requests and rapid delivery, call (972) 371–4348.

1 of 6

111799

DS1007-9 Related Products

	DS1007-9	DS1007S-11/T&R	DS1007S-10/T&R	DS1007S-3/T&R	DS1007S-6/T&R	DS1007-3	DS1007-5	DS1007-6	DS1007-8
Description	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim
Parts packaging code	DIP	SOIC	SOIC	SOIC	SOIC	DIP	DIP	DIP	DIP
package instruction	0.300 INCH, DIP-16	SOP,	SOP,	SOP,	SOP,	0.300 INCH, DIP-16	0.300 INCH, DIP-16	0.300 INCH, DIP-16	0.300 INCH, DIP-16
Contacts	16	16	16	16	16	16	16	16	16
Reach Compliance Code	not_compliant	unknown	unknown	unknown	unknown	not_compliant	not_compliant	not_compliant	not_compliant
series	1007	1007	1007	1007	1007	1007	1007	1007	1007
JESD-30 code	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16
length	19.175 mm	10.285 mm	10.285 mm	10.285 mm	10.285 mm	19.175 mm	19.175 mm	19.175 mm	19.175 mm
Logic integrated circuit type	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE
Number of functions	7	7	7	7	7	7	7	7	7
Number of taps/steps	1	1	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SOP	SOP	SOP	SOP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	240	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
programmable delay line	NO	NO	NO	NO	NO	NO	NO	NO	NO
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	2.67 mm	2.67 mm	2.67 mm	2.67 mm	4.572 mm	4.572 mm	4.572 mm	4.572 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES	YES	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Total delay nominal (td)	35 ns	14 ns	40 ns	10 ns	20 ns	10 ns	15 ns	20 ns	30 ns
width	7.62 mm	7.495 mm	7.495 mm	7.495 mm	7.495 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
JESD-609 code	e0	-	-	-	-	e0	e0	e0	e0
Encapsulate equivalent code	DIP16,.3	-	-	-	-	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3
power supply	5 V	-	-	-	-	5 V	5 V	5 V	5 V
Maximum supply current (ICC)	70 mA	-	-	-	-	70 mA	70 mA	70 mA	70 mA
Prop。Delay @ Nom-Sup	35 ns	-	-	-	-	10 ns	15 ns	20 ns	30 ns
Terminal surface	Tin/Lead (Sn/Pb)	-	-	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

Recommended Resources

Delayed self-extinguishing circuits

Circuit Optocoupler Isolation Amplifier Block Diagram

Positive and negative tracking adjustable voltage regulator circuit diagram

Output voltage fixed circuit diagram

555D/A conversion double mutually complementary frequency generator circuit

The power supply voltage is too low and the contactor closes the emergency circuit

DS1007-9 Similar Products

Part Number	Manufacturer	Description
DS1007-7	Rochester Electronics	SILICON DELAY LINE, TRUE OUTPUT, PDIP16, 0.300 INCH, DIP-16
DS1007-13	DALLAS	7-1 Silicon Delay Line
DS1007-6	DALLAS	7-1 Silicon Delay Line
DS1007-10	DALLAS	SILICON DELAY LINE, TRUE OUTPUT, PDIP16
DS1007-8	DALLAS	7-1 Silicon Delay Line
DS1007-4	DALLAS	7-1 Silicon Delay Line
DS1007-12	DALLAS	SILICON DELAY LINE, TRUE OUTPUT, PDIP16
DS1007-11	Maxim(美信半导体)	Delay Lines / Timing Elements
DS1007-14	Maxim(美信半导体)	Delay Lines / Timing Elements
DS1007-5	Maxim(美信半导体)	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16
DS1007-3	DALLAS	7-1 Silicon Delay Line
DS1007-2	Maxim(美信半导体)	Delay Lines / Timing Elements
DS1007-1	Maxim(美信半导体)	Delay Lines / Timing Elements

3*1W isolated drive solution; difficult to pass safety regulations: The FSEZ1317 solution currently being debugged: Input 85-265 Output 10V 350MA Passed EMI However, due to the limitation of the 30mm diameter round PCB board, the primary and secondary sides of the EE1...; czf0408 LED Zone

How to extract files after manual wiring in FPGA_EDITOR: How to extract files after manual wiring in FPGA_EDITOR I used the VERTIEX4 chip and manually laid out and routed it using FPGA-EDITOR to generate ncd and pcf files. But now I have a problem: I don't ...; eeleader FPGA/CPLD

How to make the semi-transparent menu above the video player in WinCE?: First of all, I think it is not realistic to use GDI, because the video is playing, and the things below are variable, and it is difficult to make semi-transparent. Secondly, use OpenGl ES? The entire...; cdj86cdj86 Embedded System

See you in April丨The 2021 Munich Shanghai Electronics Show is about to start, and pre-registration is in full swing!: Since entering China in 2002, the Munich Shanghai Electronics Fair (electronica China) has been diligently cultivating the Chinese electronics industry for nearly 20 years. With its strong brand influ...; eric_wang Talking

New moderator report, greetings to everyone: Hello everyone, I am the new moderator. I would like to greet all the experts first! I wish you all good work...I am a junior student at Hangzhou Dianzi University. I think I have good skills in micro...; 破茧佼龙 Power technology

Live Review: June 28th Datang NXP Semiconductors | Battery Management Chip Solution Design and Precautions: Live broadcast time: June 28 (Tuesday) 10:00-11:30 amLive broadcast topic: Battery management chip solution design and precautionsWatch replay: Click to watch Courseware Download Questions and Answers...; EEWORLD社区 Power technology

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components