DS1007S-11/T&R datasheet, PDF - EEWORLD Datasheet

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DS1007S-11/T&R: DescriptionSilicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16; Categorylogic logic; File Size55KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1007S-11/T&R Overview

Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16

DS1007S-11/T&R Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	unknown
series	1007
JESD-30 code	R-PDSO-G16
length	10.285 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	7
Number of taps/steps	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	2.67 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	14 ns
width	7.495 mm
Base Number Matches	1

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DS1007

7-1 Silicon Delay Line

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

All-silicon time delay

IN1

IN3

7 independent buffered delays

OUT1

OUT3

Delay tolerance ±2 ns

Four delays can be custom set between 3 ns

IN4

IN2

IN3

IN1

and 10 ns

OUT2

OUT4

OUT3

OUT1

Three delays can be custom set between 9 ns

IN4

IN2

GND

and 40 ns

OUT4

OUT2

OUT7

IN5

GND

Delays are stable and precise

OUT7

IN5

OUT5

Economical

IN7

OUT5

Auto-insertable, low profile

IN6

OUT6

IN6

OUT6

Surface mount 16-pin SOIC

DS1007 16-Pin DIP (300-mil)

DS1007S 16-Pin SOIC

Low-power CMOS

See Mech. Drawings Section

(300-mil)

TTL/CMOS-compatible

See Mech. Drawings Section

Vapor phase, IR and wave solderable

Custom specifications available

PIN DESCRIPTION

Quick turn prototypes

IN1 - IN7

- Inputs

Out1 – Out7 - Outputs

GND

- Ground

- +5 Volts

DESCRIPTION

The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas

Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an

accuracy of

±2

ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.

Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to

older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after

the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special

requests and rapid delivery, call (972) 371–4348.

1 of 6

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Description	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16	Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDIP16, 0.300 INCH, DIP-16
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim
Parts packaging code	SOIC	SOIC	SOIC	SOIC	DIP	DIP	DIP	DIP	DIP
package instruction	SOP,	SOP,	SOP,	SOP,	0.300 INCH, DIP-16	0.300 INCH, DIP-16	0.300 INCH, DIP-16	0.300 INCH, DIP-16	0.300 INCH, DIP-16
Contacts	16	16	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
series	1007	1007	1007	1007	1007	1007	1007	1007	1007
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16
length	10.285 mm	10.285 mm	10.285 mm	10.285 mm	19.175 mm	19.175 mm	19.175 mm	19.175 mm	19.175 mm
Logic integrated circuit type	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE
Number of functions	7	7	7	7	7	7	7	7	7
Number of taps/steps	1	1	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	DIP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	240
programmable delay line	NO	NO	NO	NO	NO	NO	NO	NO	NO
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.67 mm	2.67 mm	2.67 mm	2.67 mm	4.572 mm	4.572 mm	4.572 mm	4.572 mm	4.572 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	20
Total delay nominal (td)	14 ns	40 ns	10 ns	20 ns	10 ns	15 ns	20 ns	30 ns	35 ns
width	7.495 mm	7.495 mm	7.495 mm	7.495 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
JESD-609 code	-	-	-	-	e0	e0	e0	e0	e0
Encapsulate equivalent code	-	-	-	-	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3
power supply	-	-	-	-	5 V	5 V	5 V	5 V	5 V
Maximum supply current (ICC)	-	-	-	-	70 mA	70 mA	70 mA	70 mA	70 mA
Prop。Delay @ Nom-Sup	-	-	-	-	10 ns	15 ns	20 ns	30 ns	35 ns
Terminal surface	-	-	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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