SN54AC564, SN74AC564
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
D
D
D
D
D
D
2-V to 6-V V
CC
Operation
Inputs Accept Voltages to 6 V
Max t
pd
of 9 ns at 5 V
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize
PCB Layout
SN54AC564 . . . J OR W PACKAGE
SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
The ’AC564 devices are octal D-type
edge-triggered flip-flops that feature inverting
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the inverse logic levels set
up at the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54AC564 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
3D
4D
5D
6D
7D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PDIP − N
SOIC − DW
−40 C 85°C
−40°C to 85 C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AC564N
SN74AC564DW
SN74AC564DWR
SN74AC564NSR
SN74AC564DBR
SN74AC564PW
SN74AC564PWR
SNJ54AC564J
SNJ54AC564W
SNJ54AC564FK
AC564
SNJ54AC564J
SNJ54AC564W
SNJ54AC564FK
AC564
AC564
AC564
TOP-SIDE
MARKING
SN74AC564N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
2003, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
8D
GND
CLK
8Q
7Q
1
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
SN54AC564, SN74AC564
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AC564, SN74AC564
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC564
MIN
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
IOL
∆t/∆v
Low-level output current
Input transition rise or fall rate
VCC = 4.5 V
VCC = 5.5 V
VCC = 4.5 V
VCC = 5.5 V
0
0
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
0
0
MAX
6
SN74AC564
MIN
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
ns/V
mA
mA
V
V
V
V
MAX
6
UNIT
V
High-level input voltage
High-level output current
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3V
IOH = −50
µA
VOH
IOH = −12 mA
IOH = −24 mA
4.5 V
5.5 V
3V
4.5 V
5.5 V
3V
IOL = 50
µA
VOL
IOL = 12 mA
IOL = 24 mA
II
IOZ
ICC
Ci
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
4.5
TA = 25°C
MIN
TYP
MAX
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
±0.5
4
SN54AC564
MIN
2.9
4.4
5.4
2.4
3.7
4.7
0.1
0.1
0.1
0.5
0.5
0.5
±1
±5
80
MAX
SN74AC564
MIN
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1
±5
40
µA
µA
µA
pF
V
V
MAX
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
SN54AC564, SN74AC564
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
6
2.5
2
75
7.5
4.5
2.5
SN54AC564
MIN
MAX
55
7
3
2
SN74AC564
MIN
MAX
60
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
4
2
2
95
5
3.5
2.5
SN54AC564
MIN
MAX
85
5
2.5
2
SN74AC564
MIN
MAX
85
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
free-air
temperature
SN74AC564
MIN
60
16.5
15
13
12.5
14
10.5
3.5
3.5
2.5
3.5
4.5
2.5
15.5
14
12.5
12
13.5
10.5
MAX
range,
UNIT
MHz
ns
ns
ns
TA = 25°C
MIN
TYP
MAX
75
3.5
8.1
8.2
7.2
7.7
8.6
7.3
14
12.5
11.5
11
12.5
9.5
SN54AC564
MIN
55
1
1
1
1
1
1
MAX
CLK
OE
OE
Q
Q
Q
3.5
2.5
3
4
2
switching characteristics over recommended operating
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
free-air
temperature
SN74AC564
MIN
85
11.5
10.5
9.5
9.5
11.5
9
2
2
2
2
2
1.5
11.5
10.5
9.5
9.5
11.5
9
MAX
range,
UNIT
MHz
ns
ns
ns
TA = 25°C
MIN
TYP
MAX
95
2
4.9
5
5.1
5.2
5.7
4.8
10.5
9.5
9
8.5
10.5
8
SN54AC564
MIN
85
1.5
1.5
1.5
1.5
1.5
1.5
MAX
CLK
OE
OE
Q
Q
Q
2
2
1.5
2
1.5
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
50
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AC564, SN74AC564
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2
×
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
Open
500
Ω
LOAD CIRCUIT
VCC
Timing Input
tw
VCC
Input
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Data Input
tsu
50% VCC
50% VCC
0V
th
VCC
50% VCC
0V
VCC
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
50% VCC
50% VCC
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
0V
Output
Control
(low-level
enabling)
tPZL
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VCC
50% VCC
50% VCC
0V
tPLZ
50% VCC
≈V
CC
VOL + 0.3 V
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0
V
VOLTAGE WAVEFORMS
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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