HT48CA0
8-Bit Remote Type MCU
Features
·
Operating voltage: 2.2V~3.6V
·
Ten bidirectional I/O lines
·
Six Schmitt trigger input lines
·
One carrier output (1/2 or 1/3 duty)
·
On-chip crystal and RC oscillator
·
Watchdog Timer
·
1K´14 program ROM
·
32´8 data RAM
·
HALT function and wake-up feature reduce power
·
Up to 1ms instruction cycle with 4MHz system clock
·
All instructions in 1 or 2 machine cycles
·
14-bit table read instructions
·
One-level subroutine nesting
·
Bit manipulation instructions
·
62 powerful instructions
·
20/24-pin SOP package
consumption
General Description
The HT48CA0 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications. This device is
the mask version which is fully pin and functionally com-
patible with the OTP version HT48RA0A device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
HALT and wake-up functions, as well as low cost, en-
hance the versatility of this device to suit a wide range of
application possibilities such as industrial control, con-
sumer products, and particularly suitable for use in
products such as leisure products, home appliance re-
mote controllers and various subsystem controllers.
Block Diagram
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
S Y S C L K /4
In s tr u c tio n
R e g is te r
M P
M
U
X
D A T A
M e m o ry
F r e q u e n c y D iv id e r
W D T
L e v e l o r C a r r ie r
C a r r ie r C o n tr o l
P C 0 C o n tro l
P C 0 /R E M
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
M U X
P O R T B
P B
S T A T U S
P B 0 ~ P B 1
P B 2 ~ P B 7
S h ifte r
P A
O S C 2
O S
R E
V D
V S
S
S
D
C 1
A C C
P O R T A
P A 0 ~ P A 7
Rev. 1.30
1
July 16, 2003
HT48CA0
Pin Assignment
P A 1
P A 0
P A 1
P A 0
P B 1
P B 0
P C 0 /R E M
V D D
O S C 2
O S C 1
V S S
R E S
9
1 0
8
7
6
5
4
3
2
1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4
P B 5
P B 1
P B 0
P C 0 /R E M
V D D
O S C 2
O S C 1
V S S
R E S
N C
N C
9
1 0
1 1
1 2
8
7
6
5
4
3
2
1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
H T 4 8 C A 0
2 0 S O P -A
H T 4 8 C A 0
2 4 S O P -A
Pad Assignment
P B 1
2 2
P B 0
1
2
3
(0 ,0 )
O S C 2
4
P C 0 /R E M
V D D
5
6
V S S
P A 0
2 1
P A 1
2 0
P A 2
1 9
P A 3
1 8
P A 4
1 7
P A 5
1 6
1 5
1 4
1 3
1 2
P A 6
P A 7
P B 2
P B 3
O S C 1
7
R E S
8
P B 7
9
P B 6
1 0
P B 5
1 1
P B 4
* The IC substrate should be connected to VSS in the PCB layout artwork.
* The TMR pad must be bonded to VDD or VSS if the TMR pad is not used.
Pad Description
Pad No.
Pad Name
I/O
Mask Option
Wake-up
or None
Description
2-bit bidirectional input/output lines with pull-high resistors. Each bit
can be determined as NMOS output or Schmitt trigger input by soft-
ware instructions. Each bit can also be configured as wake-up input
by mask option.
Level or carrier output pin
PC0 can be set as CMOS output pin or carrier output pin by mask op-
tion.
Positive power supply
OSC1, OSC2 are connected to an RC network or a crystal (deter-
mined by mask option) for the internal system clock. In the case of
RC operation, OSC2 is the output terminal for 1/4 system clock
(NMOS open drain output).
1, 22
PB0, PB1
I/O
2
3
5
4
PC0/REM
VDD
OSC1
OSC2
O
¾
I
O
Level or
Carrier
¾
Crystal
or RC
Rev. 1.30
2
July 16, 2003
HT48CA0
Pad No.
6
7
13~8
Pad Name
VSS
RES
PB2~PB7
I/O
¾
I
I
Mask Option
¾
¾
Wake-up
or None
¾
Description
Negative power supply, ground
Schmitt trigger reset input. Active low.
6-bit Schmitt trigger input lines with pull-high resistors. Each bit can
be configured as a wake-up input by mask option.
Bidirectional 8-bit input/output port with pull-high resistors. Each bit
can be determined as NMOS output or Schmitt trigger input by soft-
ware instructions.
21~14
PA0~PA7
I/O
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+4.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
V
DD
I
DD
I
STB
V
IL1
V
IH1
V
IL2
V
IH2
I
OL
I
OH
R
PH1
R
PH2
Parameter
Operating Voltage
Operating Current
Standby Current
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
I/O Ports Sink Current
PC0/REM Ports Source Current
Pull-high Resistance of PA Port,
PB0~PB1 and RES
Pull-high Resistance of PB2~PB7
Test Conditions
V
DD
¾
3V
3V
3V
3V
3V
3V
3V
3V
3V
3V
V
OL
=0.3V
V
OH
=2.7V
¾
¾
Conditions
¾
No load, f
SYS
=4MHz
No load, system HALT
¾
¾
¾
¾
Min.
2.2
¾
¾
0
1.95
¾
¾
1.5
-1
¾
¾
Typ.
¾
0.7
¾
¾
¾
1.5
2.4
2.5
-1.5
60
60
Max.
3.6
1.5
1
1.05
3
¾
¾
¾
¾
¾
¾
Ta=25°C
Unit
V
mA
mA
V
V
V
V
mA
mA
kW
kW
A.C. Characteristics
Symbol
f
SYS
t
RES
t
SST
Parameter
System Clock
External Reset Low Pulse Width
System Start-up Timer Period
Test Conditions
V
DD
3V
¾
¾
Conditions
¾
¾
Power-up or
wake-up from HALT
Min.
400
1
¾
Typ.
¾
¾
1024
Max.
4000
¾
¾
Ta=25°C
Unit
kHz
ms
t
SYS
Note: t
SYS
=1/f
SYS
Rev. 1.30
3
July 16, 2003
HT48CA0
Functional Description
Execution Flow
The HT48CA0 system clock can be derived from a crys-
tal/ceramic resonator oscillator. It is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
Program Counter
-
PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 1024 ad-
dresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
T 1
S y s te m
C lo c k
T 2
T 3
T 4
T 1
T 2
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory
-
ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, ad-
dressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
·
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
T 3
T 4
T 1
T 2
T 3
T 4
In s tr u c tio n C y c le
P C
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
Mode
Initial reset
Skip
Loading PCL
Jump, call branch
Return from subroutine
*9
#9
S9
*8
#8
S8
@7
#7
S7
@6
#6
S6
Program Counter
*9
0
*8
0
*7
0
*6
0
*5
0
PC+2
@5
#5
S5
@4
#4
S4
@3
#3
S3
@2
#2
S2
@1
#1
S1
@0
#0
S0
*4
0
*3
0
*2
0
*1
0
*0
0
Program counter
Note:
*9~*0: Program counter bits
#9~#0: Instruction code bits
Rev. 1.30
4
July 16, 2003
HT48CA0
0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
If the stack is full and a
²CALL²
is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Data Memory
-
RAM
n 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
P ro g ra m
R O M
The data memory is designed with 42´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32´8). Most of them are read/write, but some are read
only.
The special function registers include the indirect address-
ing register (00H), the memory pointer register (MP;01H),
3 F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 4 b its
N o te : n ra n g e s fro m
0 to 3
Program memory
last page) transfer the contents of the lower-order byte
to the specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined, the other
bits of the table word are transferred to the lower por-
tion of TBLH, the remaining 2 bits are read as
²0².
The
Table Higher-order byte register (TBLH) is read only.
The table pointer (TBLP) is a read/write register (07H),
where P indicates the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. All table re-
lated instructions need 2 cycles to complete the oper-
ation. These areas may function as normal program
memory depending upon the requirements.
Stack Register
-
STACK
This is a special part of the memory used to save the
contents of the program counter (PC) only. The stack is
organized into one level and is neither part of the data
nor part of the program space, and is neither readable
nor writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
1 A
1 B
1 C
1 D
1 E
1 F
2 0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
In d ir e c t A d d r e s s in g R e g is te r
M P
A C
P C
T B
T B
C
L
L P
L H
S T A T U S
S p e c ia l P u r p o s e
D A T A M E M O R Y
P A
P B
P C
: U n u s e d
R e a d a s "0 0 "
G e n e ra l P u rp o s e
D A T A M E M O R Y
(3 2 B y te s )
3 F H
RAM mapping
Instruction(s)
TABRDC [m]
TABRDL [m]
Table Location
*9
P9
1
*8
P8
1
*7
@7
@7
*6
@6
@6
*5
@5
@5
*4
@4
@4
*3
@3
@3
*2
@2
@2
*1
@1
@1
*0
@0
@0
Table location
Note:
*9~*0: Table location bits
P9~P8: Current program counter bits
5
@7~@0: Table pointer bits
Rev. 1.30
July 16, 2003
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