The AS7C3256K16Z and AS7C3256K18Z are high performance CMOS 4 Mbit synchronous Static Random Access Memories (SRAM)
organized as 262,144 words × 16/18 bits and incorporates a two stage register-register pipeline for highest frequency on any given
technology.
This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a read command follows this write information, the system must wait for two 'dead' cycles for valid
data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-
modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two cycle read latency. Write data is
applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD
™
, write and read operations can be
used in any order without producing dead bus cycles.
The single register flow-through mode of the AS7C3256K18Z can disable output circuit registers. This allows the device to operate in 2-1-1-
1 mode rather than 3-1-1-1 found in two-stage pipeline architecture timing. The single register flow-through mode sacrifices access and
cycle times for lower latency. Consult AC timing parameters for more details.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs In pipeline
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read and write operations. When ADV is high, external addresses are ignored, and
internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be
stalled using the CEN clock enable input. If CEN is high at the rising edge of clock, all operations are effectively stalled.
The AS7C3256K18Z family operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate power supply
(V
DDQ
) that operates across 3.3V or 2.5V ranges. They are packaged in a standard 100-pin TQFP.
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Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
:ULWHHQDEOHWUXWKWDEOH
SHUE\WH
GWE
L
X
H
H
BWE
X
L
H
L
BWn
X
L
X
H
WRITEn
T
T
F
F
†
Key: X = Don’t Care, L = Low, H = High.
†
Valid read.
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Signal
CLK
A0–A17
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
FT
ZZ
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Properties
CLOCK
SYNC
SYNC
Description
Clock. All inputs except OE are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE1 is
inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more
SYNC
information.
Synchronous chip enables. Active High and active Low, respectively. Sampled on clock
SYNC
edges when ADSC is active or when CE1 and ADSP are active.
Address strobe processor. Asserted Low to load a new bus address or to enter standby
SYNC
mode.
SYNC
Address strobe controller. Asserted Low to load a new address or to enter standby mode.
SYNC
Advance. Asserted Low to continue burst read/write.
SYNC default Global write enable. Asserted Low to write all 36 bits. When High, BWE and WE0–WE3
control write enable.
This signal is internally pulled High.
= High
SYNC default Byte write enable. Asserted Low with GWE = High to enable effect of WE0–WE3 inputs.
= Low
This signal is internally pulled Low.
Write enables. Used to control write of individual bytes when GWE = High and BWE =
Low. If any of BW[a:b] is active with GWE = High and BWE = Low the cycle is a write
SYNC
cycle. If all BW[a:b] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
ASYNC
synchronously enabled.
STATIC
Count mode. When driven High, count sequence follows Intel XOR convention. When
default =
driven Low, count sequence follows linear convention.
This signal is internally pulled High.
18
High
Flow-through mode.When low, enables flow-through mode. Connect to V
DD
if unused or
STATIC
for pipelined operation.
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
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Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
+4.6
V
DDQ
+ 0.5
1.2
30
+150
+135
Unit
V
V
V
W
mA
o
C
o
C
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions may affect reliability.
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CE0
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
WRITEn
†
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
H
H
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
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Key: X = Don’t Care, L = Low, H = High.
†
See Write enable truth table for more information.
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