VP16256-27CG datasheet, PDF - EEWORLD Datasheet

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VP16256-27CG: DescriptionProgrammable FIR Filter; File Size168KB，20 Pages; ManufacturerMitel; Websitehttps://www.mitel.com

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VP16256-27CG Overview

Programmable FIR Filter

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VP16256

Programmable FIR Filter

Advance Information

Supersedes August 1997 version, DS4548 - 3.2

DS4548 - 4.0 August 1998

The VP16256 contains sixteen multiplier - accumulators, which

can be multi cycled to provide from 16 to 128 stages of digital filtering.

Input data and coefficients are both represented by 16-bit two’s

complement numbers with coefficients converted internally to 12 bits

and the results being accumulated up to 32 bits.

In 16-tap mode the device samples data at the system clock rate

of up to 40MHz. If a lower sample rate is acceptable then the number

of stages can be increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the sample clock rate

must be halved with respect to the system clock. With 128 stages the

sample clock is therefore one eighth of the system clock.

In all speed modes devices can be cascaded to provide filters of

any length, only limited by the possibility of accumulator overflow. The

32-bit results are passed between cascaded devices without any

intermediate scaling and subsequent loss of precision.

The device can be configured as either one long filter or two

separate filters with half the number of taps in each. Both networks

can have independent inputs and outputs.

Both single and cascaded devices can be operated in decimate-

by-two mode. The output rate is then half the input rate, but twice the

number of stages are possible at a given sample rate. A single device

with a 40MHz clock would then, for example, provide a 128-stage low

pass filter, with a 10MHz input rate and 5MHz output rate.

Coefficients are stored internally and can be down loaded from

a host system or an EPROM. The latter requires no additional

support, and is used in stand alone applications. A full set of

coefficients is then automatically loaded at power on, or at the request

of the system. A single EPROM can be used to provide coefficients

for up to 16 devices.

EPROM

ADDR DATA

CHANGE

COEFF

POWER-ON

RESET

RES

PIN 1

PIN 1 IDENT

208

GH208

Pin identification diagram (top view)

See Table 1 for pin descriptions and Table 2 for pinout

INPUT

DATA

16256

EPROM

SCLK

GND

OUTPUT

DATA

Fig. 1 A dual filter application

EPROM

ADDR DATA

CHANGE

COEFF

POWER-ON

RESET

RES

COEFFICIENTS

FEATURES

Sixteen MACs in a Single Device

Basic Mode is 16-Tap Filter at up to 40MHz

Sample Rates

Programmable to give up to 128 Taps with

Sampling Rates Proportionally Reducing to 5MHz

16-bit Data and 32-bit Accumulators

Can be configured as One Long Filter or Two Half-

Length Filters

Decimate-by-two Option will Double the Filter

Length

Coefficients supplied from a Host System or a local

EPROM

208-Pin Plastic PowerQuad PQ2 Package

APPLICATIONS

High Performance Commercial Digital Filters

Matrix Multiplication

Correlation

High Performance Adaptive Filtering

16256

ANALOG

INPUT

ADC

EPROM

CLKOP

SCLK

GND

OUTPUT

DATA

ORDERING INFORMATION

VP16256-27/CG/GH1N

27MHz, Commercial

PowerQuad PQ2 package (GH208)

VP16256-40/CG/GH1N

40MHz, Commercial

PowerQuad PQ2 package (GH208)

plastic

Fig. 2 Typical system application

VP16256

Signal

DA15:0

DB15:0

X31:0

16-bit data input bus to Network A.

Description

Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a

cascaded chain. Input to Network B in the dual filter modes.

Expansion input bus in the single filter mode. Connected to the previous filter output in a cascaded chain.

The inputs are not used on a single device system or on the Termination device in a cascaded chain. The

X bus provides the output from Network B in both dual modes.

In single filter mode this bus holds the main device output. In dual mode it holds the output from Network A.

Filter enable. The first high present on an SCLK rising edge defines the first data sample. The control

whilst valid data is being received and must be low if FRUN is high.

Delayed filter enable. This output is connected to the Filter Enable input of the next device in a cascaded

chain when moving towards the termination device and with multiple stand-alone EPROM-loaded

configurations. It is used to coordinate the control logic within each device.

Selects either the upper or lower set of coefficients for Bank Swap. A low selects the lower bank, a high

the upper bank.

In EPROM load mode, when high this signal allows continuous filter operations to occur without the need for

the initial FEN edge. If the device is not a single, interface or master device then this pin must be tied low.

A low on this signal on the SCLK rising edge will clear all the internal accumulators. DCLR need only remain

low for a single cycle, signal BUSY will indicate when the internal clearing is complete. After a clear the

device must be re-synchronised to the data stream using FEN. It is recommended that FEN is taken low

at the same time as clear. FEN may then be taken high to synchronise the data stream once BUSY has

returned low.

16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the

text.

Coefficient address bus. In the EPROM mode A7:0 are address outputs for an EPROM. In the remote host

mode they are inputs from the host. A7 is not used when coefficients are loaded as 16-bit words.

This pin is similar in operation to A7:0 and provides a higher order address bit. When low the coefficients

are loaded, when high the control register is loaded.

In the remote mode this pin is an input which when low enables the load operation. In the EPROM mode

it is an output which provides the write enable for other slave devices.

This pin is always an input and must also be low for the internal write operation to occur.

When this pin is tied low, coefficients are loaded as two 8-bit bytes. When the pin is high they are loaded

as 16-bit words. In the EPROM mode this pin is ignored.

When this pin is tied low coefficients are loaded as bytes from an external EPROM. The device outputs

an address on A7:0. When the pin is high coefficients must be loaded from a remote master. They can then

be transferred individually rather than as a complete set.

The main system clock; all operations are synchronous with this clock. The clock rate must be either 1, 2,

4, or 8 times the required data sampling rate. The factor used depends on the required filter length.

This output, when used to enable SCLK, can provide a data sampling clock. It has the effect of dividing

the SCLK rate by 1, 2, 4 or 8 depending on the filter mode selected.

Tri-state enable for the F bus. When high the outputs will be high impedance. OEN is registered onto the

device and does not therefore take effect until the first SCLK rising edge

A high on this signal indicates that the device is completing internal operations and is not yet able to accept

new data. The signal is used during automatic EPROM loading, reset and accumulator clearing.

When this pin is low the control logic and accumulators are reset. In the EPROM mode it will initiate a load

sequence when it goes high.

F31:0

FEN

DFEN

SWAP

FRUN

DCLR

C15:0

A7:0

CCS

WEN

BYTE

EPROM

SCLK

CLKOP

OEN

BUSY

RES

NOTES

1. Unused buses (e.g. X31:0 when the device is configured in single or termination mode) can be set to any value. They should however be

maintained at a valid logic level to avoid an increase in power consumption.

2. To ensure correct input voltage thresholds are maintained all the V

and GND pins must be connected to adequate power and ground planes.

Table 1 Pin descriptions

VP16256-27CG Related Products

	VP16256-27CG	VP16256-40CGGH1N	VP16256-40	VP16256-40CG	VP16256-27CGGH1N	VP16256	VP16256-27
Description	Programmable FIR Filter	Programmable FIR Filter	Programmable FIR Filter	Programmable FIR Filter	Programmable FIR Filter	Programmable FIR Filter	Programmable FIR Filter

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