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EP2C35U484C8

Description
FPGA, 903 CLBS, 402.5 MHz, PBGA256
CategoryProgrammable logic devices    Programmable logic   
File Size957KB,168 Pages
ManufacturerAltera (Intel)
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EP2C35U484C8 Overview

FPGA, 903 CLBS, 402.5 MHz, PBGA256

EP2C35U484C8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codeBGA
package instructionUBGA-484
Contacts484
Reach Compliance Code_compli
ECCN code3A991
Other featuresALSO REQUIRES 3.3 SUPPLY
maximum clock frequency402.5 MHz
JESD-30 codeS-PBGA-B484
JESD-609 codee0
length19 mm
Humidity sensitivity level3
Configurable number of logic blocks2076
Number of entries322
Number of logical units33216
Output times306
Number of terminals484
Maximum operating temperature85 °C
Minimum operating temperature
organize2076 CLBS
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA484,22X22,40
Package shapeSQUARE
Package formGRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)220
power supply1.2,1.5/3.3,3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2.2 mm
Maximum supply voltage1.25 V
Minimum supply voltage1.15 V
Nominal supply voltage1.2 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width19 mm
Section I. Cyclone II
Device Family Data Sheet
This section provides information for board layout designers to
successfully layout their boards for Cyclone
®
II devices. It contains the
required PCB layout guidelines, device pin tables, and package
specifications.
This section includes the following chapters:
Chapter 1. Introduction
Chapter 2. Cyclone II Architecture
Chapter 3. Configuration & Testing
Chapter 4. Hot Socketing & Power-On Reset
Chapter 5. DC Characteristics and Timing Specifications
Chapter 6. Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Altera Corporation
Section I–1
Preliminary

EP2C35U484C8 Related Products

EP2C35U484C8 EP2C20AF256I8N EP2C50F672C8N EP2C70F672C8N EP2C70F896C8N EP2C20F484C8N EP2C20F484I8N
Description FPGA, 903 CLBS, 402.5 MHz, PBGA256 FPGA, 1172 CLBS, 402.5 MHz, PBGA256 FPGA, 3158 CLBS, 402.5 MHz, PBGA672 FPGA, 903 CLBS, 402.5 MHz, PBGA256 FPGA, 4276 CLBS, 402.5 MHz, PBGA896 FPGA, 1172 CLBS, 402.5 MHz, PBGA484 FPGA, 1172 CLBS, 402.5 MHz, PBGA484
Is it lead-free? Contains lead Lead free Lead free Lead free Lead free Lead free Lead free
Is it Rohs certified? incompatible conform to conform to conform to conform to conform to conform to
Parts packaging code BGA BGA BGA BGA BGA BGA BGA
package instruction UBGA-484 LEAD FREE, FBGA-256 LEAD FREE, FBGA-672 LEAD FREE, FBGA-672 LEAD FREE, FBGA-896 LEAD FREE, FBGA-484 LEAD FREE, FBGA-484
Contacts 484 256 672 672 896 484 484
Reach Compliance Code _compli unknow unknow unknow unknow unknow unknow
Other features ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY ALSO REQUIRES 3.3 SUPPLY
maximum clock frequency 402.5 MHz 402.5 MHz 402.5 MHz 402.5 MHz 402.5 MHz 402.5 MHz 402.5 MHz
JESD-30 code S-PBGA-B484 S-PBGA-B256 S-PBGA-B672 S-PBGA-B672 S-PBGA-B896 S-PBGA-B484 S-PBGA-B484
JESD-609 code e0 e1 e1 e1 e1 e1 e1
length 19 mm 17 mm 27 mm 27 mm 31 mm 23 mm 23 mm
Humidity sensitivity level 3 3 3 3 3 3 3
Configurable number of logic blocks 2076 1172 3158 4276 4276 1172 1172
Number of entries 322 152 450 422 622 315 315
Number of logical units 33216 18752 50528 68416 68416 18752 18752
Output times 306 136 434 406 606 299 299
Number of terminals 484 256 672 672 896 484 484
organize 2076 CLBS 1172 CLBS 3158 CLBS 4276 CLBS 4276 CLBS 1172 CLBS 1172 CLBS
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FBGA LBGA BGA BGA BGA BGA BGA
Encapsulate equivalent code BGA484,22X22,40 BGA256,16X16,40 BGA672,26X26,40 BGA672,26X26,40 BGA896,30X30,40 BGA484,22X22,40 BGA484,22X22,40
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY, FINE PITCH GRID ARRAY, LOW PROFILE GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Celsius) 220 260 260 260 260 260 260
power supply 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V 1.2,1.5/3.3,3.3 V
Programmable logic type FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 2.2 mm 1.55 mm 2.6 mm 2.6 mm 2.6 mm 2.6 mm 2.6 mm
Maximum supply voltage 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V
Minimum supply voltage 1.15 V 1.15 V 1.15 V 1.15 V 1.15 V 1.15 V 1.15 V
Nominal supply voltage 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Terminal surface Tin/Lead (Sn63Pb37) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form BALL BALL BALL BALL BALL BALL BALL
Terminal pitch 0.8 mm 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature 30 40 40 40 40 40 30
width 19 mm 17 mm 27 mm 27 mm 31 mm 23 mm 23 mm
Maker Altera (Intel) Altera (Intel) - Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel)
ECCN code 3A991 - 3A991 3A991 3A001.A.7.A - 3A991
Maximum operating temperature 85 °C - 85 °C 85 °C 85 °C 85 °C -
Temperature level OTHER - OTHER OTHER OTHER OTHER -
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