IDT74FCT810BTEG datasheet, PDF

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IDT74FCT810BTEG: DescriptionLow Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDFP20, CERPACK-20; Categorylogic logic; File Size132KB，6 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT74FCT810BTEG Overview

Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDFP20, CERPACK-20

IDT74FCT810BTEG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	DFP
package instruction	DFP,
Contacts	20
Reach Compliance Code	compliant
Other features	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1.2NS
series	FCT
Input adjustment	SCHMITT TRIGGER
JESD-30 code	R-GDFP-F20
JESD-609 code	e3
Load capacitance (CL)	50 pF
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs	5
Number of terminals	20
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	4.5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.7 ns
Maximum seat height	2.3368 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.92 mm

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	IDT74FCT810BTEG	IDT74FCT810CTDG	IDT74FCT810CTLG	IDT74FCT810BTDG	IDT74FCT810BTLG	IDT74FCT810CTEG
Description	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDFP20, CERPACK-20	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDIP20, CERDIP-20	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CQCC20, LCC-20	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDIP20, CERDIP-20	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CQCC20, LCC-20	Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CDFP20, CERPACK-20
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	DFP	DIP	QLCC	DIP	QLCC	DFP
package instruction	DFP,	DIP,	QCCN,	DIP,	QCCN,	DFP,
Contacts	20	20	20	20	20	20
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
Other features	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1.2NS	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1NS	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1NS	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1.2NS	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1.2NS	ONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1NS
series	FCT	FCT	FCT	FCT	FCT	FCT
Input adjustment	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER
JESD-30 code	R-GDFP-F20	R-GDIP-T20	S-CQCC-N20	R-GDIP-T20	S-CQCC-N20	R-GDFP-F20
JESD-609 code	e3	e3	e3	e3	e3	e3
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1	1	1	1	1
Number of inverted outputs	5	5	5	5	5	5
Number of terminals	20	20	20	20	20	20
Actual output times	5	5	5	5	5	5
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	DFP	DIP	QCCN	DIP	QCCN	DFP
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR
Package form	FLATPACK	IN-LINE	CHIP CARRIER	IN-LINE	CHIP CARRIER	FLATPACK
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
propagation delay (tpd)	4.5 ns	4.3 ns	4.3 ns	4.5 ns	4.5 ns	4.3 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.7 ns	0.6 ns	0.6 ns	0.7 ns	0.7 ns	0.6 ns
Maximum seat height	2.3368 mm	5.08 mm	2.54 mm	5.08 mm	2.54 mm	2.3368 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	FLAT	THROUGH-HOLE	NO LEAD	THROUGH-HOLE	NO LEAD	FLAT
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	QUAD	DUAL	QUAD	DUAL
Maximum time at peak reflow temperature	30	40	30	40	30	30
width	6.92 mm	7.62 mm	8.89 mm	7.62 mm	8.89 mm	6.92 mm
length	-	25.34 mm	8.89 mm	25.34 mm	8.89 mm	-

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