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T4
16
PMR280UN
N-channel TrenchMOS ultra low level FET
Rev. 2 — 3 February 2012
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode Field-Effect Transistor (FET) in ultra small
Surface-Mounted Device (SMD) plastic package using TrenchMOS technology.
1.2 Features and benefits
Surface mounted package
Low on-state resistance
Footprint 63% smaller than SOT23
Low threshold voltage
1.3 Applications
Driver circuits
Switching in portable appliances
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
V
GS
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
gate-source voltage
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 0.2 A; T
j
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
sp
= 25 °C; V
GS
= 4.5 V
Min
-
-
-8
-
Typ
-
-
-
280
Max
20
0.98
8
340
Unit
V
A
V
mΩ
Static characteristics
2. Pinning information
Table 2.
Pin
1
2
3
Pinning information
Symbol Description
G
S
D
gate
source
drain
1
2
S
017aaa253
Simplified outline
3
Graphic symbol
D
G
SOT416 (SC-75)
NXP Semiconductors
PMR280UN
N-channel TrenchMOS ultra low level FET
3. Ordering information
Table 3.
Ordering information
Package
Name
PMR280UN
SC-75
Description
plastic surface-mounted package; 3 leads
Version
SOT416
Type number
4. Marking
Table 4.
Marking codes
Marking code
R5
Type number
PMR280UN
5. Limiting values
Table 5.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; pulsed; t
p
≤
10 µs
T
sp
= 25 °C; V
GS
= 4.5 V
T
sp
= 100 °C; V
GS
= 4.5 V
T
sp
= 25 °C; pulsed; t
p
≤
10 µs
T
sp
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-8
-
-
-
-
-55
-55
-
-
Max
20
20
8
0.98
0.62
1.97
0.53
150
150
0.44
0.88
Unit
V
V
V
A
A
A
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PMR280UN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 February 2012
2 of 13
NXP Semiconductors
PMR280UN
N-channel TrenchMOS ultra low level FET
120
I
der
(%)
80
03aa25
120
P
der
(%)
80
03aa17
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
10
ID
(A)
03an10
Limit RDSon = VDS / ID
tp = 10
μ
s
1
100
μ
s
1 ms
10-1
DC
10 ms
100 ms
10-2
10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMR280UN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 February 2012
3 of 13
NXP Semiconductors
PMR280UN
N-channel TrenchMOS ultra low level FET
6. Thermal characteristics
Table 6.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
Conditions
Min
-
Typ
-
Max
235
Unit
K/W
103
03an29
Zth(j-sp)
(K/W)
δ
= 0.5
102
0.2
0.1
0.05
0.02
single pulse
10
10-4
10-3
10-2
10-1
1
tp (s)
10
tp
T
t
P
δ
=
tp
T
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PMR280UN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 February 2012
4 of 13
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