L64364NL datasheet, PDF - EEWORLD Datasheet

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L64364NL: DescriptionATM/SONET/SDH Segmentation and Reassembly Device, CMOS, PQFP240,; CategoryWireless rf/communication Telecom circuit; File Size3MB，444 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com

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L64364NL Overview

ATM/SONET/SDH Segmentation and Reassembly Device, CMOS, PQFP240,

L64364NL Parametric

Parameter Name	Attribute value
Maker	LSC/CSI
package instruction	QFP, QFP240,1.3SQ,20
Reach Compliance Code	unknown
JESD-30 code	S-PQFP-G240
Number of terminals	240
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP240,1.3SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	1040 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD

L64364NL Preview

TECHNICAL

MANUAL

L64364

ATMizer

II+

ATM-SAR Chip

February 2001

R14008.A

This document contains proprietary information of LSI Logic Corporation. The

information contained herein is not to be used by or disclosed to third parties

without the express written permission of an ofﬁcer of LSI Logic Corporation.

Document DB14-000037-02, Second Edition (February 2001)

This document describes LSI Logic Corporation’s L64364 ATMizer

II+ ATM-SAR

Chip and will remain the ofﬁcial reference source for all revisions of this product

until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein

at any time without notice. LSI Logic does not assume any responsibility or

liability arising out of the application or use of any product described herein,

except as expressly agreed to in writing by LSI Logic; nor does the purchase or

use of a product from LSI Logic convey a license under any patent rights,

copyrights, trademark rights, or any other of the intellectual property rights of

LSI Logic or third parties.

TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, CoreWare, G10, MiniRISC, and ATMizer are

registered trademarks of LSI Logic Corporation. All other brand and product

names may be trademarks of their respective companies.

Preface

This book is the primary reference and technical manual for the L64364

ATMizer

II+ ATM-SAR Chip. It contains a complete functional

description of the L64364 and includes complete physical and electrical

speciﬁcations for the L64364.

Audience

This book assumes that you have some familiarity with the concepts of

Asynchronous Transfer Mode (ATM), data communications,

microprocessors, and related support devices. The people who beneﬁt

from this book are:

•

Organization

Engineers and managers who are evaluating the L64364 for possible

use in ATM applications.

Engineers who are designing the L64364 into a system.

Software developers writing software for the L64364.

This book has the following chapters:

•

Chapter 1,

Introduction,

provides an overview of the ATMizer II+

ATM-SAR Chip and lists its features.

Chapter 2,

Functional Overview,

describes the ATMizer II+ chip on

a functional block level.

Chapter 3,

Signal Descriptions,

lists and describes all of the

input/output signals of the ATMizer II+ chip.

Chapter 4,

ATM Processing Unit,

describes the architecture,

instruction set, registers, cache memory, memory map, interrupts,

exceptions, and boot procedures for the ATM Processing Unit.

Preface

iii

•

Chapter 5,

Enhanced DMA,

describes the data structures used by

the EDMA, the EDMA commands, its registers, and its operation in

AAL0 and AAL5 modes.

Chapter 6,

ATM Cell Interface,

describes the ATM cell size and

layout, the cell descriptor, registers, Cell Buffer Manager, receiver,

transmitter, Utopia polling schemes, and loopback mode for the ATM

Cell Interface.

Chapter 7,

Scheduler Unit,

describes the Scheduler Unit’s modes of

operation, command execution, and registers.

Chapter 8,

Timer Unit,

describes how the timer clocks are selected,

the timer registers, and time-out events.

Chapter 9,

PCI Interface,

describes the PCI registers, master and

slave transactions, and how the ATMizer II+ chip balances bus

usage.

Chapter 10,

Secondary Bus Memory Controller,

describes the

controller conﬁguration, discusses bus performance considerations,

and describes the operation of the individual controllers.

Chapter 11,

System Clock,

discusses clock selection and describes

its synthesis using a phase-locked loop.

Chapter 12,

JTAG Interface,

describes the JTAG instructions

supported by the L64364 and the bit order of the L64364 boundary

scan chain.

Chapter 13,

Speciﬁcations,

provides AC timing ﬁgures, electrical

requirements, pinout information, and package information for the

ATMizer II+ chip.

Appendix A,

provides a brief summary of all of

the registers in the ATMizer II+ chip and includes page number

references for their descriptions.

Appendix B,

The ATM Cell,

describes the layout and ﬁelds in the

ATM cell header and the AAL5 trailer.

Appendix C,

Glossary of Abbreviations,

lists the abbreviations

used in the manual and deﬁnes them.

•

Preface

Related Publications

LSI Logic’s

MiniRISC

CW4011 Superscalar Microprocessor Core

Technical Manual,

Order No. C14040

ATM Forum - Utopia Level 1 and Level 2, V1.0,

af-phy-0039.00

PCI Local Bus Speciﬁcation 2.1

IEEE 1149.1, Standard Test Access Port and Boundary Scan Architecture

Conventions Used in This Manual

The following signal naming conventions are used throughout this manual:

•

Signal names are in uppercase characters. Active-LOW signals have

a lowercase “n” at the end of the signal name (for example, RESETn)

while active-HIGH signals do not.

Multiple control signals such as external interrupts are grouped (for

example, EXT_INTn[5:0]), but they are treated as control signals.

Signal names, commands, and register bits and ﬁelds are courier.

All CW4011 core and CW4011 shell interface signals are

unidirectional.

•

The word

assert

means to drive a signal true or active. The word

deassert

means to drive a signal false or inactive. The word

set

means

to change a bit (in registers, descriptors, etc.) from logical 0 to logical 1.

The word

clear

means to change a bit from 1 to 0.

Hexadecimal numbers are indicated by the preﬁx “0x”—for example,

0x32CF. Binary numbers are indicated by the preﬁx “0b”—for example,

0b0011.0010.1100.1111. The hexadecimal form is used as much as

possible for all numbers with four or more bits.

The L64364 requires over 100 internal and external registers. These are

described in the appropriate chapters and sections. Register references

in other sections of the manual are followed by the page number of their

description in parenthesis. In addition, Appendix A lists the registers by

functional area, includes their addresses, and provides page number

references to their descriptions.

Preface

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

L64364NL Related Products

	L64364NL
Description	ATM/SONET/SDH Segmentation and Reassembly Device, CMOS, PQFP240,
Maker	LSC/CSI
package instruction	QFP, QFP240,1.3SQ,20
Reach Compliance Code	unknown
JESD-30 code	S-PQFP-G240
Number of terminals	240
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP240,1.3SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	1040 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD

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