84330AY-03LFT datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 84330AY-03LFT

84330AY-03LFT: DescriptionClock Generator, PQFP32; CategoryThe embedded processor and controller Microcontrollers and processors; File Size315KB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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84330AY-03LFT Overview

Clock Generator, PQFP32

84330AY-03LFT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	QFP, QFP32,.35SQ,32
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD

84330AY-03LFT Preview

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MH

, L

ITTER

, C

RYSTAL

-3.3V

IFFERENTIAL

LVPECL F

REQUENCY

YNTHESIZER

EATURES

•

Fully integrated PLL, no external loop filter requirements

Two differential 3.3V LVPECL output

Crystal oscillator interface: 10MHz to 25MHz

Output frequency range: 41.67MHz to 700MHz

VCO range: 250MHz to 700MHz

Parallel or I

C interface for programming M and N dividers

during power-up

Supports Spread Spectrum Clocking (SSC)

Center spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2%

Up/Down spread: selectable 0.5%, 1.0%, 1.5%, 2%,

2.5%, 3%, 3.5%, 4%

RMS Period jitter: 9ps (maximum)

Cycle-to-cycle jitter: 40ps (maximum)

3.3V supply voltage

0°C to 70°C ambient operating temperature

Industrial temperature information available upon request

Available in both standard and lead-free RoHS-compliant

packages

ENERAL

ESCRIPTION

The ICS84330-03 is a general purpose, dual

output high frequency synthesizer and a mem-

HiPerClockS™

ber of the HiPerClockS™ family of High Perfor-

mance Clock Solutions from ICS. The VCO

operates at a frequency range of 250MHz to

700MHz. The VCO and output frequency can be pro-

grammed using the I

C interface. The output can be config-

ured to divide the VCO frequency by 1, 2, 3, 4, and 6.

Additionally, the device suppor ts spread spectrum clock-

ing (SSC) for minimizing Electromagnetic Interference

(EMI). The low cycle-cycle jitter and broad frequency

range of the ICS84330-03 make it an ideal clock gen-

erator for a variety of demanding applications which

require high performance.

•

LOCK

IAGRAM

Pullup

VCO_SEL

Pullup

XTAL_IN

SSIGNMENT

nQ0

nQ1

SCL

SDA

32 31 30 29 28 27 26 25

VCO_SEL

OSC

ADDR_SEL

CCA

ICS84330-03

32-Lead LQFP

Y package

7mm x 7mm x 1.4mm

body package

Top View

XTAL_OUT

FREF_EXT

Pulldown

CCA

÷16

FREF_EXT

XTAL_SEL

XTAL_IN

XTAL_SEL

Pullup

9 10 11 12 13 14 15 16

XTAL_OUT

nP_LOAD

PLL

Phase Detector

VCO

÷M

÷2

÷1

nQ0

÷2

÷3

÷4

÷6

nQ1

ADDR_SEL

Pulldown

SDA

SCL

nP_LOAD

Pullup

M0:M8

M0:M7 = Pulldown, M8 = Pullup

84330AY-03

Pulldown

C Parallel Interface

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MH

, L

ITTER

, C

RYSTAL

-3.3V

IFFERENTIAL

LVPECL F

REQUENCY

YNTHESIZER

The programming mode is controlled by the nP_LOAD pin.

When this pin is low, The M, N values are set by the logic

values on the M, N pins. If nP_LOAD is HIGH, the M, N

dividers can be changed using the I

C serial programming

interface.

The I

C control registers are defined below:

The ICS84330-03 uses either a parallel interface or indus-

try standard I

C interface to control the programming of the

internal dividers. The power on defaults are summarized as

follows:

256

Output

Q0/nQ0 output at 267MHz

(using a 16.667MHz crystal)

Q1/nQ1 output at 133MHz

(using a 16.667MHz crystal)

SSC Mode:

Off

Parallel Mode:

Data Byte 0

Control Bit

Power-up Default Value

Data Byte 1

Control Bit

Power-up Default Value

Not

Used

Not

Used

Not

Used

Not

Used

Not

Used

Data Byte 2

Control Bit

Power-up Default Value

Down

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

C A

DDRESSING

The ICS84330-03 can be set to decode one of two addresses

to minimize the chance of address conflict on the I

C bus. The

ADDR_SEL (pin 3) = 0 Default

Bit 5

Bit 4

Bit 3

Bit 2

address that is decoded is controlled by the setting of the

ADDR_SEL pin (pin 3).

Bit 7

Bit 6

Bit 1

Bit 0

R/ W

Bit 7

Bit 6

ADDR_SEL (pin 3) = 1

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

84330AY-03

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MH

, L

ITTER

, C

RYSTAL

-3.3V

IFFERENTIAL

LVPECL F

REQUENCY

YNTHESIZER

mum SCL frequency is greater than 10MHz which is more

than sufficient for standard I

C clock speeds.

C I

NTERFACE

- P

ROTOCOL

The ICS84330-03 is a slave-only device and uses the stan-

dard I

C protocol as shown in the below diagrams. The maxi-

SCL

SDA

START

Valid Data

Acknowledge

STOP

START (ST)

– defined as high-to-low transition on SDA while holding SCL HIGH.

DATA

- Between START and STOP cycles, SDA is synchronous with SCL.

Data may change only when SCL is LOW and must be stable when SCL is HIGH.

ACKNOWLEDGE (AK)

– SDA is driven LOW before the SCL rising edge and

held LOW until the SCL falling edge.

STOP (SP)

– defined as low-to-high transition on SDA while holding SCL HIGH.

C I

NTERFACE

- A W

RITE

XAMPLE

A serial transfer to the ICS84330-03 always consists of an

address cycle followed by 4 data bytes: 1 dummy byte fol-

lowed by 3 data bytes. Any additional bytes beyond the 4 data

bytes will not be acknowledged and the ICS84330-03 will

leave the data bus HIGH. These extra bits will not be loaded

into the serial control register. Once the 4 Data bytes are loaded

1 Bit

and the master generates a stop condition, the values in the

serial control register are latched into the M divider, N divider,

and control bits and the device will smoothly slew to the new

frequency and any changes to the state of the control bits will

take effect.

R/W

1 Bit

Slave Address: 7 Bits

Refer to page 2 for address choices based on ADDR_SEL pin setting

Dummy Byte 0: 8 Bits

1 Bit

Data Byte 0: 8 Bits

1 Bit

Data Byte 1: 8 Bits

Not

Used

Not

Used

Not

Used

Not

Used

1 Bit

Data Byte 2: 8 Bits

Down

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

1 Bi t

1 Bit

Data Byte values latched into control registers here.

84330AY-03

↑

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MH

, L

ITTER

, C

RYSTAL

-3.3V

IFFERENTIAL

LVPECL F

REQUENCY

YNTHESIZER

has been selected and the M-divider value will toggle be-

tween the programmed M value, and M-SS at a 32kHz rate.

When both the UP and DN bits are HIGH, then center-

spread has been selected and the M-divider will toggle

between M+SS and M-SS at a 32kHz rate. The table below

shows the desired SS value to achieve 0.5%, 1% and 1.5%

spread at selected VCO frequencies. To disable Spread

Spectrum operation, program both the UP and DN bits to

LOW. Spread Spectrum operation will also be disabled when

the nP_LOAD input is LOW.

PREAD

PECTRUM

PERATION

NOTE: The functional description that follows used a

16.6667MHz crystal with an M divide value of 160.

Spread Spectrum operation is controlled by I

C Data Byte

2, Spread Spectrum Control Register. Bits SSC0 – SSC5

(SS) of the register are a subtrahend to the M-divider for

down-spread, and they are an addend and a subtrahend to

the M-divider for center-spread. When the UP bit is HIGH,

then up-spread has been selected and the M-divider value

will toggle between the programmed M value, and M+SS at

a 32kHz rate. When the DN bit is HIGH, then down-spread

ABLE

1A. SS M

ODE

UNCTION

ABLE

SSC7

SSC6

SS Mode

Off

Down-Spread

Up-Spread

Center-Spread

ABLE

1B. U

OWN

PREAD

ONFIGURATION

Up- or Down-Spread SS Value

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

Spread %

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

ABLE

1C. C

ENTER

PREAD

ONFIGURATION

Center-Spread SS Value

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

Spread (±) %

0.50

1.00

1.50

2.00

84330AY-03

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MH

, L

ITTER

, C

RYSTAL

-3.3V

IFFERENTIAL

LVPECL F

REQUENCY

YNTHESIZER

The programmable features of the ICS84330-03 support

two input modes to program the M divider and N output

divider. The two input operational modes are parallel and

Figure 1

shows the timing diagram for parallel mode. In

parallel mode the nP_LOAD input is LOW. The data on

inputs M0 through M8 and N0 through N1 is passed

directly to the M divider and N output divider. On the LOW-

to-HIGH transition of the nP_LOAD input, the data is latched

and the M divider remains loaded until the next LOW tran-

sition on nP_LOAD or until an I

C event occurs. The rela-

tionship between the VCO frequency, the crystal frequency

and the M divider is defined as follows: fVCO = fxtal x 2M

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Func-

tion Table. Valid M values for which the PLL will achieve

lock are defined as 120

≤

336. The frequency out is

defined as follows: fout = fVCO = fxtal x 2M

UNCTIONAL

ESCRIPTION

NOTE: The functional description that follows describes op-

eration using a 16.6667MHz crystal. Valid PLL loop divider

values for different crystal or input frequencies are defined

in the Input Frequency Characteristics, Table 7, NOTE 1.

The ICS84330-03 features a fully integrated PLL and

therefore requires no external components for setting the

loop bandwidth. A quartz crystal is used as the input to the

on-chip oscillator. The output of the oscillator is divided by

16 prior to the phase detector.

The phase detector and the M divider force the VCO output

frequency to be 2M times the reference frequency by

adjusting the VCO control voltage. Note that for some

values of M (either too high or too low), the PLL will not

achieve lock. The output of the VCO is scaled by a divider

prior to being sent to each of the LVPECL output buffers.

The divider provides a 50% output duty cycle.

ARALLEL

OADING

M0:M8, N0:N1

M, N

nP_LOAD

Time

IGURE

1. P

ARALLEL

OAD

PERATIONS

84330AY-03

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

84330AY-03LFT Related Products

	84330AY-03LFT	84330AY-03LF
Description	Clock Generator, PQFP32	Clock Generator, PQFP32
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Reach Compliance Code	compliant	compliant
JESD-30 code	S-PQFP-G32	S-PQFP-G32
JESD-609 code	e3	e3
Humidity sensitivity level	3	3
Number of terminals	32	32
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP
Encapsulate equivalent code	QFP32,.35SQ,32	QFP32,.35SQ,32
Package shape	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD

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