The AS7C181024LL is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 131,072 words × 8
bits. It is designed for portable applications where fast data access, long battery life, and simple interfacing are desired.
65$0
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55*/70/100 ns with output enable access times (t
OE
) of 25*/35/50 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory
systems.
When CE1 is HIGH or CE2 is LOW, the device enters standby mode. The AS7C181024LL is guaranteed not to exceed 2.0
µW
power
consumption in standby mode with the inputs static. This device offers data retention.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
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In the AS7C181024LL design, priority was placed on low power while maintaining moderately high performance. To reduce standby and
data retention current, a 6-transistor memory cell was utilized. Active power was reduced considerably over traditional designs by using
Intelliwatt™ power reduction circuitry. With Intelliwatt™, SRAM powers down unused circuits between access operations, resulting in
longer cycle times and lower duty cycles, and providing incremental power savings. During periods of inactivity, Intelliwatt™ SRAM power
consumption can be as low as fully de-activated standby power, even though the chip is enabled. This power savings, both in active and
inactive modes, results in longer battery life, and better product marketability. All chip inputs and outputs are TTL-compatible, and operation
is from a single 1.8V supply. The device is packaged in common industry standard packages.
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Parameter
Voltage on any input pin
Voltage on any I/O pin
Power dissipation
Storage temperature (plastic)
DC output current
Symbol
V
tIN
V
tI/O
P
D
T
stg
I
out
Min
–0.5
–0.5
–
–55
–
Max
+2.5
V
DD
+ 0.4
1.0
+150
20
Unit
V
V
W
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
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CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
H
L
X
Data
High Z
High Z
High Z
D
out
D
in
Mode
Standby (I
SB
, I
SB1
)
Standby (I
SB
, I
SB1
)
Output disable
Read
Write
Key: X = Don’t Care, L = Low, H = High
* For availability of 55 ns device, contact Alliance.
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Parameter
Supply voltage
Input voltage
Symbol
V
DD
V
SS
V
IH
Min
1.65
0.0
0.7 × V
DD
–0.5
Nominal
1.8
0.0
–
–
Max
1.95
0.0
V
DD
+ 0.5
0.3 × V
DD
Unit
V
V
V
V
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V
IL
†V min = –3.0V for pulse width less than 10 ns.
IL
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1
-55*
Parameter
Input leakage
current
Output leakage
current
Output voltage
Symbol
|
I
LI
|
|
I
LO
|
V
OL
V
OH
Test conditions
V
DD
= Max,
V
in
= V
SS
to V
DD
CE1 = V
IH
or
CE2 = V
IL
,
V
DD
= Max,
V
out
= V
SS
to V
DD
I
OL
= 100 µA, V
DD
= Min
I
OH
= –100 µA, V
DD
= Min
Min
–
Max
1
-70
Min
–
Max
1
-100
Min
–
Max
1
Unit
µA
µA
V
V
–
–
0.8×V
DD
1
0.2
–
–
–
0.8×V
DD
1
0.2
–
–
–
0.8×V
DD
1
0.2
–
* For availability of 55 ns device, contact Alliance.
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-55*
Parameter
Operating, active
Operating, static
Symbol
I
DD
I
DD1
I
SB
Standby power supply
current
I
SB1
Test conditions
CE1
≤
V
IL
, CE2=V
IH
, f = f
Max
I
OUT
= 0 mA
CE
=
V
SS
, V
DD
= Max, f = 0,
I
OUT
= 0 mA
CE1
≥
V
IH
or CE2 = V
IL,
f = f
Max
CE1
≥
V
DD
–0.2V or CE2
≤
0.2V,
V
IN
≤
0.2V or V
IN
≥
V
DD
–0.2V,
f=0
Min
–
–
–
–
Max
19
20
20
1
-70
Min
–
–
–
–
Max
15
20
20
1
-100
Min
–
–
–
–
Max
10
20
20
1
Unit
mA
µA
µA
µA
* For availability of 55 ns device, contact Alliance.
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2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
I/O
I 0+]7
D
5RRPWHPSHUDWXUH9
''
9
Test conditions
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
A, CE1, CE2, WE, OE V
in
= 0V
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-55*
Parameter
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
Min
55
–
–
–
3
3
–
3
–
0
–
Max
–
55
55
25
–
–
25
–
25
–
55
Min
70
–
–
–
3
3
–
3
–
0
–
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
* For availability of 55 ns device, contact Alliance.
-70
Max
–
70
70
35
–
–
35
–
35
–
70
-100
Min
100
–
–
–
3
3
–
3
–
0
–
Max
–
100
100
50
–
–
50
–
50
–
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
3
Notes
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Rising input
Falling input
Undefined output/don’t care
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t
RC
Address
t
AA
D
out
Data valid
t
OH
5HDGZDYHIRUP
3,6,7,9,12
5HDGZDYHIRUP
3,6,8,9,12
t
RC1
CE1
CE2
t
OE
OE
t
OLZ
t
ACE1, tACE2
D
out
t
CLZ1, tCLZ2
Current
supply
t
PU
50%
Data valid
t
PD
50%
t
OHZ
t
CHZ1, tCHZ2
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I
CC
I
SB
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11
55*
Parameter
Write cycle time
Chip enable (CE1 & CE2) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in High Z
Output active from write end
* For availability of 55 ns device, contact Alliance.
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