EP20K200CQC208-8X datasheet, PDF

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EP20K200CQC208-8X: DescriptionLoadable PLD, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size2MB，102 Pages; ManufacturerAltera (Intel)

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EP20K200CQC208-8X Overview

Loadable PLD, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208

EP20K200CQC208-8X Parametric

Parameter Name	Attribute value
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	FQFP,
Contacts	208
Reach Compliance Code	unknown
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
Number of I/O lines	136
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature
organize	136 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Programmable logic type	LOADABLE PLD
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
Temperature level	OTHER
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

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APEX 20KC

Programmable Logic

Device

Data Sheet

March 2001, ver. 1.0

Features...

Preliminary

Information

Programmable logic device (PLD) manufactured using a 0.15-µm all-

layer copper-metal fabrication process

–

25 to 35% faster design performance than APEX

20KE devices

–

Pin-compatible with APEX 20KE devices

–

High-performance, low-power copper interconnect

–

MultiCore

architecture integrating look-up table (LUT) logic

and embedded memory

–

LUT logic used for register-intensive functions

–

Embedded system blocks (ESBs) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port

RAM, and content-addressable memory (CAM)

High-density architecture

–

100,000 to 1.5 million typical gates (see

Table 1)

–

Up to 51,840 logic elements (LEs)

–

Up to 442,368 RAM bits that can be used without reducing

available logic

Note (1)

EP20K400C

1,052,000

400,000

16,640

104

212,992

-7, -8, -9

1,664

502

Table 1. APEX 20KC Device Features

Feature

Maximum

system gates

Typical gates

LEs

ESBs

Maximum RAM

bits

PLLs

(2)

Speed grades

(3)

Maximum

macrocells

Maximum user

I/O pins

Notes:

(1)

(2)

(3)

EP20K100C

263,000

100,000

4,160

53,248

-7, -8, -9

416

252

EP20K200C

526,000

200,000

8,320

106,496

-7, -8, -9

832

382

EP20K600C

1,537,000

600,000

24,320

152

311,296

-7, -8, -9

2,432

624

EP20K1000C

1,772,000

1,000,000

38,400

160

327,680

-7, -8, -9

2,560

708

EP20K1500C

2,392,000

1,500,000

51,840

216

442,368

-7, -8, -9

3,456

808

The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to

57,000 additional gates.

PLL: phase-locked loop.

The -7 speed grade provides the fastest performance.

Altera Corporation

A-DS-APEX20KC-01

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