November 2008
HYS72T128301EP–[25F/3S]–C2
HYS72T256300EP–[25F/3S]–C2
HYS72T256321EP–[25F/3S]–C2
240-Pin VLP Registered DDR2 SDRAM Modules
DDR2 SDRAM
EU RoHS Compliant
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYS72T[128/256]3xxEP–[25F/3S]–C2
Registered DDR2 SDRAM Module
HYS72T128301EP–[25F/3S]–C2, HYS72T256300EP–[25F/3S]–C2, HYS72T256321EP–[25F/3S]–C2
Revision History: 2008-11, Rev. 1.00
Page
All
Subjects (major changes since last revision)
Added Package Outline for Rawcard AC and T and removed product type HYS72T[128/256]3xxEP-2.5-C2 and
adapted to internet edition.
New Document.
Previous Revision: Rev. 0.50, 2008-02
All
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qag_techdoc_A4, 4.21, 2008-05-13
02182008-GHCD-FPBL
2
Internet Data Sheet
HYS72T[128/256]3xxEP–[25F/3S]–C2
Registered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-pin Very Low Profile Registered DDR2 SDRAM modules product family with parity
bit for address and control bus and describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
μs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
Serial Presence Detect with E
2
PROM.
Dimensions (nominal): 18.30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Cards 'T', 'AC'
and 'Z'.
RoHS compliant products
1)
.
• 240-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory
modules.
• One rank 128M
×
72, 256M
×
72 and , two rank 256M
×
72
module organization, and 128M
×
8, 256M
×
4 chip
organization.
• 2-GB, 1-GB Modules built with 1-Gbit DDR2 SDRAMs in
chipsize packages PG-TFBGA-60.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
DDR2
PC2
–25F
–800D
–6400D
5–5–5
–3S
–667D
–5300D
5–5–5
200
266
333
15
15
45
60
18
Unit
Note
t
CK
MHz
MHz
MHz
ns
ns
ns
ns
ns
1)2)
Precharge-All (8 banks) command period
15
1) This
t
PREA
value is the minimum value at which this chip will be functional.
f
CK3
f
CK4
f
CK5
t
RCD
t
RP
t
RAS
t
RC
t
PREA
200
266
400
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 1.00, 2008-11
02182008-GHCD-FPBL
3
Internet Data Sheet
HYS72T[128/256]3xxEP–[25F/3S]–C2
Registered DDR2 SDRAM Module
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
1.2
Description
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB. The DIMMs feature serial presence detect based on
a serial E
2
PROM device using the 2-pin I
2
C protocol. The first
128 bytes are programmed with configuration data and are
write protected; the second 128 bytes are available to the
customer.
The Qimonda HYS72T[128/256]3xxEP–[25F/3S]–C2 module
family are Very Low Profile (VLP) Registered DIMM modules
“RDIMMs” with parity bit for address and control bus and
18.30 mm height based on DDR2 technology. DIMMs are
available as ECC modules
in 128M
×
72 (1-GB),
256M
×
72 (2-GB) in organization and density, intended for
mounting into 240-pin connector sockets.
The memory array is designed with 1-Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (5-5-5)
HYS72T256321EP-25F-C2
2GB 2R×8 PC2–6400P–555–12–T0
HYS72T256300EP-25F-C2
2GB 1R×4 PC2–6400P–555–12–ZZ
HYS72T128301EP-25F-C2
1GB 1R×8 PC2–6400P–555–12–AC0
PC2-5300 (5-5-5)
HYS72T256321EP-3S-C2
HYS72T256300EP-3S-C2
HYS72T128301EP-3S-C2
2GB 2R×8 PC2–5300P–555–12–T0
2GB 1R×4 PC2–5300P–555–12–ZZ
1GB 1R×8 PC2–5300P–555–12–AC0
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
1Gbit (×8)
1Gbit (×4)
1Gbit (×8)
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
1Gbit (×8)
1Gbit (×4)
1Gbit (×8)
Compliance Code
2)
Description
SDRAM Technology
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–T0" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "T".
TABLE 3
Address Format
DIMM
Density
2GB
2GB
1GB
Module
Organization
256M
×
72
256M
×
72
128M
×
72
Memory
Ranks
2
1
1
ECC/
Non-ECC
ECC
ECC
ECC
# of SDRAMs # of row/bank/column
bits
18
18
9
14/3/10
14/3/11
14/3/10
Raw
Card
T
Z
AC
Rev. 1.00, 2008-11
02182008-GHCD-FPBL
4
Internet Data Sheet
HYS72T[128/256]3xxEP–[25F/3S]–C2
Registered DDR2 SDRAM Module
TABLE 4
Components on Modules
Product Type
1)2)
HYS72T256321EP
HYS72T256300EP
HYS72T128301EP
DRAM Components
1)
HYB18T1G800C2F
HYB18T1G400C2F
HYB18T1G800C2F
DRAM Density
1Gbit
1Gbit
1Gbit
DRAM Organisation
128M
×
8
256M
×
4
128M
×
8
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.00, 2008-11
02182008-GHCD-FPBL
5