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Datasheet> All Categories > Discrete semiconductor> The transistor> JANSR2N7410
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JANSR2N7410

Description
Power Field-Effect Transistor, 3.5A I(D), 100V, 0.6ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3
CategoryDiscrete semiconductor    The transistor   
File Size90KB，9 Pages
ManufacturerInternational Rectifier （ Infineon ）
Websitehttp://www.irf.com/
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JANSR2N7410 Overview

Power Field-Effect Transistor, 3.5A I(D), 100V, 0.6ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3

JANSR2N7410 Parametric

Parameter NameAttribute value
MakerInternational Rectifier （ Infineon ）
Parts packaging codeBCY
package instructionCYLINDRICAL, O-MBCY-W3
Contacts4
Reach Compliance Codeunknown
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage100 V
Maximum drain current (ID)3.5 A
Maximum drain-source on-resistance0.6 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-205AF
JESD-30 codeO-MBCY-W3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Package body materialMETAL
Package shapeROUND
Package formCYLINDRICAL
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)10.5 A
Certification statusNot Qualified
GuidelineMIL-19500/638
surface mountNO
Terminal formWIRE
Terminal locationBOTTOM
transistor applicationsSWITCHING
Transistor component materialsSILICON

JANSR2N7410 Preview

JANSR2N7410
Formerly FSL110R4
January 2002
3.5A, 100V, 0.600 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Discrete Products Operation of Fairchild Corporation
has developed a series of Radiation Hardened MOSFETs
specifically designed for commercial and military space
applications. Enhanced Power MOSFET immunity to Single
Event Effects (SEE), Single Event Gate Rupture (SEGR) in
particular, is combined with 100K RADS of total dose hard-
ness to provide devices which are ideally suited to harsh
space environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.
The Fairchild portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula-
tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be oper-
ated directly from integrated circuits.
BRAND
JANSR2N7410
Features
• 3.5A, 100V, r
DS(ON)
= 0.600Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 0.3nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cm
2
Ordering Information
PART NUMBER
JANSR2N7410
PACKAGE
TO-205AF
Also available at other radiation and screening levels. See us
on the web, Fairchild’s home page: http://www.fairchild-
semi.com. Contact your local Fairchild Sales Office for addi-
tional information.
Die Family TA17616.
MIL-PRF-19500/638.
Symbol
Package
TO-205AF
D
G
S
©2002 Fairchild Semiconductor Corporation
JANSR2N7410 Rev. B
JANSR2N7410
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JANSR2N7410
100
100
3.5
2.5
10.5
±20
15
6
0.12
10.5
3.5
10.5
-55 to 150
300
1.0
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
100
-
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 12V
V
GS
= 0V to 2V
V
DD
= 50V,
I
D
= 3.5A
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.520
-
-
-
-
-
-
7.6
-
2.2
4.3
-
-
MAX
-
5.0
4.0
-
25
250
100
200
2.21
0.600
0.960
30
60
30
55
15
8.5
0.62
2.8
4.9
8.3
175
UNITS
V
V
V
V
µA
µA
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 80V,
V
GS
= 0V
V
GS
=
±20V
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
Gate to Source Leakage Current
I
GSS
Drain to Source On-State Voltage
Drain to Source On Resistance
V
DS(ON)
r
DS(ON)12
V
GS
= 12V, I
D
= 3.5A
I
D
= 2.5A,
V
GS
= 12V
T
C
= 25
o
C
T
C
= 125
o
C
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on slash sheet)
Gate Charge at 12V
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Gate Charge Drain
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(12)
Q
g(TH)
Q
gs
Q
gd
R
θ
JC
R
θ
JA
V
DD
= 50V, I
D
= 3.5A,
R
L
= 14.3Ω, V
GS
= 12V,
R
GS
= 7.5Ω
©2002 Fairchild Semiconductor Corporation
JANSR2N7410 Rev. B
JANSR2N7410
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 3.5A
I
SD
= 3.5A,dI
SD
/dt = 100A/µs
MIN
0.6
-
TYP
-
-
MAX
1.8
220
UNITS
V
ns
Electrical Specifications up to 100K R A D
C
= 25
o
C, Unless Otherwise Specified
T
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 80V
V
GS
= 12V, I
D
= 3.5A
V
GS
= 12V, I
D
= 2.5A
MIN
100
1.5
-
-
-
-
MAX
-
4.0
100
25
2.21
0.600
UNITS
V
V
nA
µA
V
Ω
Single Event Effects (SEB, SEGR)
(Note 4)
ENVIRONMENT
(NOTE 5)
ION
SPECIES
Ni
Br
Br
Br
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm
2
(typical), T
C
= 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
26
37
37
37
TYPICAL
RANGE (µ)
43
36
36
36
APPLIED
V
GS
BIAS
(V)
-20
-10
-15
-20
(NOTE 6)
MAXIMUM
V
DS
BIAS
(V)
100
100
80
50
TEST
Single Event Effects Safe Operating
Area
SYMBOL
SEESOA
©2002 Fairchild Semiconductor Corporation
JANSR2N7410 Rev. B
JANSR2N7410
Typical Performance Curves
120
100
80
V
DS
(V)
60
40
20
0
0
TEMP = 25
o
C
-5
-10
V
GS
(V)
-15
-20
-25
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
Unless Otherwise Specified
LET = 26MeV/mg/cm
2
, RANGE = 43µ
LET = 37MeV/mg/cm
2
, RANGE = 36µ
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
LIMITING INDUCTANCE (HENRY)
1E-3
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
4
100
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10
100µs
T
C
= 25
o
C
2
I
D
, DRAIN CURRENT (A)
3
I
D
, DRAIN (A)
1ms
1
10ms
100ms
1
0
-50
0
50
100
150
0.1
0.1
T
C
, CASE TEMPERATURE (
o
C)
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2002 Fairchild Semiconductor Corporation
JANSR2N7410 Rev. B
JANSR2N7410
Typical Performance Curves
Unless Otherwise Specified
(Continued)
2.5
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 2.5A
2.0
12V
Q
G
NORMALIZED r
DS(ON)
1.5
Q
GS
V
G
Q
GD
1.0
0.5
CHARGE
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
THERMAL RESPONSE (Z
θ
JC
)
1
0.5
0.1
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
P
DM
NORMALIZED
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (s)
10
0
10
1
0.001
10
-5
10
-4
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
I
AS
, AVALANCHE CURRENT (A)
10
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
1
1E-5
1E-4
1E-3
t
AV
, TIME IN AVALANCHE (ms)
1E-2
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
©2002 Fairchild Semiconductor Corporation
JANSR2N7410 Rev. B
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