ASAHI KASEI
[AK4364]
96kHz 24Bit
∆Σ
DAC with PLL and DIT
AK4364
GENERAL DESCRIPTION
The AK4364 is a stereo CMOS D/A Converter and Phase Locked Loop for use in digital video broadcast
set-top box applications or DVD. The DAC signal outputs are single-ended and are analog filtered to
remove out of band noise. Therefore no external filters are required. The PLL provides selectable
sampling clock frequencies locked to the 27MHz recovered MPEG clock. The AK4364 has also Digital
Audio Interface Transmitter.
FEATURES
o
Stereo
∆Σ
DAC
o
S/(N+D): 90dB@5V
o
DR:
102dB@5V
o
S/N:
102dB@5V
o
Multiple Sampling Frequencies:
16kHz, 22.05kHz, 24kHz (Half speed)
32kHz, 44.1kHz, 48kHz (Normal speed)
64kHz, 88.2kHz, 96kHz (Double speed)
o
On-Chip Low Jitter Analog PLL:
Multiple Master Clock Frequencies generated from 27MHz
256fs/384fs/512fs/768fs/1024fs/1536fs
for Half speed
256fs/384fs/512fs/768fs
for Normal speed
128fs/192fs/256fs/384fs
for Double speed
o
Master Clock: PLL / External
o
Data Input Formats:
LSB justified / MSB justified / I
2
S selectable
o
Selectable Function:
Soft Mute
Digital Attenuator (256 Steps)
Digital De-emphasis (44.1kHz/48kHz/32kHz)
o
Output Mode: Stereo, Mono, Reverse, Mute
o
On-Chip Digital Audio Interface Transmitter:
Compatible with S/PDIF, IEC958, AES/EBU
& EIAJ CP1201 consumer mode
o
Input Level:TTL/CMOS Selectable
o
Output Level: 3.0Vpp@5V
o
Control mode: 3-wire Serial / I
2
C Bus
o
Low Power Dissipation: 80mW@5V
o
Small 24pin VSOP Package
o
Power Supply: 2.7∼5.5V
o
Ta: -40∼85°C
MS0014-E-01
-1-
2000/07
ASAHI KASEI
[AK4364]
n
Block Diagram
CAD1 CAD0 I2C
CSN CCLK CDTI
MCKI
MCKO
FLT
TX
DIT
AVDD
LRCK
BICK
SDTI
Serial Input
Interface
PLL &
Clock Generator
AVSS
VCOM
TTL
ATT
DVDD
DVSS
8X
Interpolator
8X
Interpolator
∆Σ
Modulator
∆Σ
Modulator
LPF
AOUTL
Mixer
ATT
LPF
AOUTR
DZF
PDN
Figure 1. 3-wire Serial Control Mode (I2C = “L”)
CAD1 CAD0 I2C
CSN
SCL
SDA
MCKI
MCKO
FLT
TX
DIT
AVDD
LRCK
BICK
SDTI
Serial Input
Interface
PLL &
Clock Generator
AVSS
VCOM
TTL
ATT
DVDD
DVSS
8X
Interpolator
8X
Interpolator
∆Σ
Modulator
∆Σ
Modulator
LPF
AOUTL
Mixer
ATT
LPF
AOUTR
DZF
PDN
Figure 2. I
2
C Bus Control Mode (I2C = “H”)
MS0014-E-01
-2-
2000/07
ASAHI KASEI
[AK4364]
n
Ordering Guide
AK4364VF
AKD4364
-40∼+85°C
Evaluation Board
24pin VSOP
n
Pin Layout
MCKO
TX
DVDD
DVSS
MCKI
BICK
SDTI
LRCK
PDN
CSN
SCL/CCLK
SDA/CDTI
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
DZF
FLT
AVDD
AVSS
VCOM
AOUTL
AOUTR
CAD1
CAD0
I2C
TTL
TST
Top
View
19
18
17
16
15
14
13
MS0014-E-01
-3-
2000/07
ASAHI KASEI
[AK4364]
PIN/FUNCTION
No.
1
Pin Name
MCKO
I/O
O
Description
Master Clock Output Pin
EXT = “0”: System clock is output from PLL circuit (PLL mode),
EXT = “1”: Same frequency as MCKI is output (External mode)
Transmit Channel Output Pin
Digital Power Supply Pin, +2.7∼+5.5V
Digital Ground Pin, 0V
System Clock Input Pin
EXT = “0”: 27MHz (PLL mode), EXT = “1”: Other frequency (External mode)
Serial Data Clock Pin
Serial Data Input Pin
Serial Input Channel Clock Pin
Power-Down Pin
When “L”, the circuit is in power-down mode.
The AK4364 should always be reset upon power-up.
Chip Select Pin at 3-wire Serial control mode
This pin should be connected to DVDD at I
2
C Bus control mode.
Control Clock Pin at I
2
C bus control mode
Control Clock Pin at 3-wire serial control mode
Control Data Input/Output Pin at I
2
C Bus control mode
Control Data Input Pin at 3-wire serial control mode
Test pin
This pin should be connected to DVSS.
Digital Input Level Select Pin
“L”: CMOS, “H”: TTL
Control Mode Select Pin
“L”: 3-wire Serial, “H”: I
2
C Bus
Chip Address Select 0 Pin
Chip Address Select 1 Pin
Rch Analog Output Pin
Lch Analog Output Pin
Common Voltage Output Pin, AVDD/2
Used for analog common voltage.
Large external capacitor is used to reduce power supply noise.
Analog Ground Pin
Analog Power Supply Pin
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AVSS with one resister and one capacitor in series.
( See “SYSTEM DESIGN”.)
Zero Input Detect Pin
When SDTI follows a total 8192 LRCK cycles with “0” input data or RSTN = “0”,
this pin goes to “H”.
2
3
4
5
6
7
8
9
TX
DVDD
DVSS
MCKI
BICK
SDTI
LRCK
PDN
O
-
-
I
I
I
I
I
10
11
12
13
14
15
16
17
18
19
20
CSN
SCL
CCLK
SDA
CDTI
TST
TTL
I2C
CAD0
CAD1
AOUTR
AOUTL
VCOM
I
I
I
I/O
I
I
I
I
I
I
O
O
O
21
22
23
AVSS
AVDD
FLT
-
-
O
24
DZF
O
Note: No input pins should be left floating.
MS0014-E-01
-4-
2000/07
ASAHI KASEI
[AK4364]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
|AVSS-DVSS|
(Note 2)
Input Current (any pins except for supplies)
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Symbol
AVDD
DVDD
∆GND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-
-
-0.3
-0.3
-40
-65
max
6.0
6.0
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
Note:1. All voltages with respect to ground.
2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies
3V operation (TTL = “L”)
(Note 3)
Analog
Digital
5V operation (TTL = “H”)
Analog
Digital
Symbol
AVDD
DVDD
AVDD
DVDD
min
2.7
2.7
4.5
4.5
typ
3.0
3.0
5.0
5.0
max
5.5
3.6 or AVDD
5.5
AVDD
Units
V
V
V
V
Note:1. All voltages with respect to ground.
3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0014-E-01
-5-
2000/07
京公网安备 11010802033920号
EEWORLD
