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U406-E3

Description
Small Signal Field-Effect Transistor, N-Channel, Junction FET
CategoryDiscrete semiconductor    The transistor   
File Size49KB,5 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
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U406-E3 Overview

Small Signal Field-Effect Transistor, N-Channel, Junction FET

U406-E3 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerVishay
package instruction,
Reach Compliance Codeunknown
FET technologyJUNCTION
JESD-609 codee3
Humidity sensitivity level1
Maximum operating temperature200 °C
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)0.3 W
surface mountNO
Terminal surfaceMatte Tin (Sn)
SST/U401 Series
Vishay Siliconix
Monolithic N-Channel JFET Duals
SST404
SST406
PRODUCT SUMMARY
Part Number
U401
SST/U404
SST/U406
U401
U404
U406
V
GS(off)
(V)
–0.5 to –2.5
–0.5 to –2.5
–0.5 to –2.5
V
(BR)GSS
Min (V)
–40
–40
–40
g
fs
Min (mS)
1
1
1
I
G
Typ (pA)
–2
–2
–2
jV
GS1
– V
GS2
j
Max (mV)
5
15
40
FEATURES
D
D
D
D
D
D
Monolithic Design
High Slew Rate
Low Offset/Drift Voltage
Low Gate Leakage: 2 pA
Low Noise
High CMRR: 102 dB
BENEFITS
D
D
D
D
D
D
Tight Differential Match vs. Current
Improved Op Amp Speed, Settling Time Accuracy
Minimum Input Error/Trimming Requirement
Insignificant Signal Loss/Error Voltage
High System Sensitivity
Minimum Error with Large Input Signal
APPLICATIONS
D
Wideband Differential Amps
D
High-Speed,Temp-Compensated,
Single-Ended Input Amps
D
High-Speed Comparators
D
Impedance Converters
DESCRIPTION
The SST/U401 series of high-performance monolithic dual
JFETs features extremely low noise, tight offset voltage and
low drift over temperature specifications, and is targeted for
use in a wide range of precision instrumentation applications.
This series has a wide selection of offset and drift
specifications with the U401 featuring a 5-mV offset and
10-mV/_C drift.
The U series, hermetically sealed TO-71 package is available
with full military processing (see Military Information). The SST
series SO-8 package provides ease of manufacturing, and the
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods (see
Packaging Information).
For similar high-gain products in TO-78 packaging, see the
2N5911/5912 data sheet.
TO-71
Narrow Body SOIC
S
1
D
1
G
1
NC
1
2
3
4
8
7
6
5
NC
G
2
D
2
S
2
G
1
Top View
SST404, SST406
Top View
U401, U404, U406
D
1
2
3
4
S
2
S
1
1
6
5
G
2
D
2
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Lead Temperature (
1
/
16
” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C
Storage Temperature :
U Prefix . . . . . . . . . . . . . . . . . . . . . –65 to 200_C
SST Prefix . . . . . . . . . . . . . . . . . . . –55 to 150_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C
Power Dissipation :
Per Side
a
. . . . . . . . . . . . . . . . . . . . . . . . 300 mW
Total
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
For applications information see AN106.
Document Number: 70247
S-04031—Rev. F, 04-Jun-01
www.vishay.com
8-1

U406-E3 Related Products

U406-E3 U404-E3
Description Small Signal Field-Effect Transistor, N-Channel, Junction FET Small Signal Field-Effect Transistor, N-Channel, Junction FET
Is it Rohs certified? conform to conform to
Reach Compliance Code unknown unknown
FET technology JUNCTION JUNCTION
JESD-609 code e3 e3
Humidity sensitivity level 1 1
Maximum operating temperature 200 °C 200 °C
Polarity/channel type N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 0.3 W 0.3 W
surface mount NO NO
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
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