GS81302R19E-375IT datasheet, PDF

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GS81302R19E-375IT: DescriptionDDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size1MB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS81302R19E-375IT Overview

DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

GS81302R19E-375IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	150994944 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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Preliminary

GS81302R19/37E-400/375

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaCIO DDR-II+

Burst of 4 SRAM

400 MHz–375 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

The GS81302R19/37E are built in compliance with the

SigmaCIO DDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302R19/37E SigmaCIO SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302R19/37E SigmaCIO DDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Common I/O SigmaCIO DDR-II+ B4 RAMs always transfer

data in four packets. When a new address is loaded, A0 and A1

preset an internal 2 bit linear address counter. The counter

increments by 1 for each beat of a burst of four data transfer.

The counter always wraps to 00 after reaching 11, no matter

where it starts.

Rev: 1.00 10/2007

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS81302R19/37E-400/375

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs

are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated

in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is

possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are

inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from

loading read or write command

inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.

SigmaCIO DDR-II B4 SRAM Read Cycles

The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst

transfer in

response to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins

are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined

reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces

data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data

is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of

four transfers per address load.

SigmaCIO DDR-II B4 SRAM Write Cycles

The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst

transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/

W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is

checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the

rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst

of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the

next rising edge of K#, for a total of four transfers per address load.

Rev: 1.00 10/2007

5/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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