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BU-65142D3-260K

Description
Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQIP78, CERAMIC, QIP-78
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size247KB,26 Pages
ManufacturerData Device Corporation
Download Datasheet Parametric View All

BU-65142D3-260K Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQIP78, CERAMIC, QIP-78

BU-65142D3-260K Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerData Device Corporation
Parts packaging codeQFP
package instructionQIP,
Contacts78
Reach Compliance Codecompliant
Address bus width11
boundary scanNO
maximum clock frequency16 MHz
letter of agreementMIL STD 1553
Maximum data transfer rate0.125 MBps
External data bus width16
JESD-30 codeR-CQIP-P78
JESD-609 codee0
low power modeNO
Number of serial I/Os2
Number of terminals78
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height5.33 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose175k Rad(Si) V
width41.91 mm
uPs/uCs/peripheral integrated circuit typeSERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
BU-65142 and BUS-65142 SERIES*
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
DESCRIPTION
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU).
The device is based upon two DDC
custom ICs, which includes two
monolithic bi-polar low power trans-
ceivers and one CMOS protocol
containing data buffers and timing
control logic. It supports all 13 mode
codes for dual redundant operation,
any combination of which can be ille-
galized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series spe-
cial features. A 14-bit built-in-test
word register stores RTU information,
and sends it to the Bus Controller in
response to the Mode Command
Transmit Bit Word. The BUS-65142
Series performs continuous on-line
wraparound self-test, and provides
four error flags to the host CPU.
Inputs are provided for host CPU con-
trol of 6 bits of the RTU Status Word.
Its
small
hermetic
package,
-55°C to +125°C operating tempera-
ture range, and complete RTU opera-
tion make the BUS-65142 ideal for
most MIL-STD-1553 applications
requiring hardware or microprocessor
subsystems.
FEATURES
Complete Integrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
Multiple Ordering Options;
+5V (Only), +5V/-15V, and +5V/-12V
Direct Interface to Systems With
No Processor
Radiation Tolerant Version
Available
Space Qualified Version Available
High Reliability Screening Available
*
(Note:
BUS-65142 is NOT recommended for new design, use BU-61703/05 Simple System RT for new designs.
BU-65142 is NOT recommended for new design, consult factory or local representative for more information)
DATA
BUS A
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
BUFFER
DB0-DB15
BUF ENA
DTREQ
DTGRT
DTACK
DTSTR
R/W
WATCHDOG
TIMEOUT
TRANSFER
CONTROLS
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
CURRENT
WORD
COUNTER
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
M
U
X
A0-A4
A5-A10
DAT/CMD
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
NBGT
INCMD
BITEN
STATEN
GBR
COMMAND
LATCH
RT ADDRESS
+
PARITY
STATUS
REGISTER
16 MHz CLOCK
ERROR FLAGS
TIMING FLAGS
DDC CUSTOM CHIP
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
©
1988, 1999 Data Device Corporation
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