PDM41024LA25P datasheet, PDF - EEWORLD Datasheet

PDM41024LA25P: DescriptionStandard SRAM, 128KX8, 25ns, CMOS, PDIP32; Categorystorage storage; File Size385KB，8 Pages; ManufacturerParadigm Technology Inc

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PDM41024LA25P Overview

Standard SRAM, 128KX8, 25ns, CMOS, PDIP32

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Paradigm Technology Inc
package instruction	DIP, DIP32,.4
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	25 ns
I/O type	COMMON
JESD-30 code	R-PDIP-T32
JESD-609 code	e0
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.4
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.0005 A
Minimum standby current	2 V
Maximum slew rate	0.135 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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