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M2V12S40TP-7

Description
Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
Categorystorage    storage   
File Size417KB,49 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
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M2V12S40TP-7 Overview

Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54

M2V12S40TP-7 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee0
length22.22 mm
memory density536870912 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8
Maximum standby current0.001 A
Maximum slew rate0.26 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
MITSUBISHI LSIs
SDRAM (Rev.1.1)
MITSUBISHI
Single Data Rate
ELECTRIC
M2V12S20/ 30/ 40 TP -6, -6L, -7, -7L
512M Synchronous DRAM
Feb. '02
DESCRIPTION
M2V12S20TP is a 4-bank x 33,554,432-word x 4-bit,
M2V12S30TP is a 4-bank x 16,777,216-word x 8-bit,
M2V12S40TP is a 4-bank x 8,388,608-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V12S20/30/40TP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6)
and are suitable for main memory or graphic memory in computer systems.
FEATURES
-Single 3.3v + 0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8)/ A0-9(x16)
- LVTTL Interface
-Both 54-pin TSOP Package
M2V12S*0TP: 0.8mm lead pitch 54-pin TSOP Package
-Low Power for the Self Refresh Current ICC6 :4mA (-6L,-7L)
Max. Frequency
@CL2
Max. Frequency
@CL3
Standard
M2V12S20/30/40TP-6,-6L
100MHz
133MHz
PC133 (CL3)
M2V12S20/30/40TP-7,-7L
100MHz
100MHz
PC100 (CL2)
Contents are subject to change without notice.
MITSUBISHI ELECTRIC
-1-

M2V12S40TP-7 Related Products

M2V12S40TP-7 M2V12S20TP-6L M2V12S40TP-6L M2V12S30TP-6 M2V12S30TP-6L
Description Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54 Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54 Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54 Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54 Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible
Maker Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi
Parts packaging code TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
package instruction TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32
Contacts 54 54 54 54 54
Reach Compliance Code unknown unknown unknown unknown unknow
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 6 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz
I/O type COMMON COMMON COMMON COMMON COMMON
interleaved burst length 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
JESD-30 code R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54
JESD-609 code e0 e0 e0 e0 e0
length 22.22 mm 22.22 mm 22.22 mm 22.22 mm 22.22 mm
memory density 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bi
Memory IC Type SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
memory width 16 4 16 8 8
Number of functions 1 1 1 1 1
Number of ports 1 1 1 1 1
Number of terminals 54 54 54 54 54
word count 33554432 words 134217728 words 33554432 words 67108864 words 67108864 words
character code 32000000 128000000 32000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C
organize 32MX16 128MX4 32MX16 64MX8 64MX8
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
Encapsulate equivalent code TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192 8192 8192
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
self refresh YES YES YES YES YES
Continuous burst length 1,2,4,8 1,2,4,8,FP 1,2,4,8 1,2,4,8,FP 1,2,4,8,FP
Maximum standby current 0.001 A 0.001 A 0.001 A 0.001 A 0.001 A
Maximum slew rate 0.26 mA 0.28 mA 0.28 mA 0.28 mA 0.28 mA
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
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