ICS93735YF-T datasheet, PDF - EEWORLD Datasheet

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ICS93735YF-T: DescriptionPLL Based Clock Driver, 93735 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, MO-118, SSOP-48; Categorylogic logic; File Size151KB，8 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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ICS93735YF-T Overview

PLL Based Clock Driver, 93735 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, MO-118, SSOP-48

ICS93735YF-T Parametric

Parameter Name	Attribute value
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	48
Reach Compliance Code	unknown
series	93735
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G48
length	15.875 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	10
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.098 ns
Maximum seat height	2.8 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
width	7.5 mm

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Integrated

Circuit

Systems, Inc.

ICS93735

DDR Phase Lock Loop Zero Delay Clock Buffer

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

• Low skew, low jitter PLL clock driver

• Max frequency supported = 266MHz (DDR 533)

• I

C for functional and output control

• Feedback pins for input to output synchronization

• Spread Spectrum tolerant inputs

• 3.3V tolerant CLK_INT input

Switching Characteristics:

• CYCLE - CYCLE jitter (66MHz): <120ps

• CYCLE - CYCLE jitter (>100MHz): <65ps

• CYCLE - CYCLE jitter (>200MHz): <75ps

• OUTPUT - OUTPUT skew: <100ps

• Output Rise and Fall Time: 500ps - 700ps

• DUTY CYCLE: 49.5% - 50.5%

Pin Configuration

Functionality

OUTPUTS

AVDD

CLK_INT

CLKT

CLKC

FB_OUTT

2.5V (nom)

< offset freq* offset freq* offset freq* offset freq*

GND

* The offset frequency is ~ 20 MHz, varying somewhat from part to part.

INPUTS

PLL State

off

Bypassed/off

48-Pin SSOP

Block Diagram

FB_OUTT

CLKT0

CLKC0

CLKT1

CLKC1

SCLK

SDATA

Control

Logic

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

CLKT5

CLKC5

FB_INT

CLK_INT

PLL

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0579F—06/14/06

ICS93735YF-T Related Products

	ICS93735YF-T	ICS93735YFLF-T
Description	PLL Based Clock Driver, 93735 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, MO-118, SSOP-48	PLL Based Clock Driver, 93735 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
Parts packaging code	SSOP	SSOP
package instruction	SSOP,	SSOP,
Contacts	48	48
Reach Compliance Code	unknown	unknown
series	93735	93735
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G48	R-PDSO-G48
length	15.875 mm	15.875 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of terminals	48	48
Actual output times	10	10
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.098 ns	0.098 ns
Maximum seat height	2.8 mm	2.8 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL
width	7.5 mm	7.5 mm

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