K7N163645A
K7N161845A
Document Title
512Kx36 & 1Mx18 Pipelined NtRAM
TM
512Kx36 & 1Mx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
1.
1.
1.
2.
1.
Initial document.
Add JTAG Scan Order
Add x32 org and industrial temperature .
Add 165FBGA package
Speed bin merge.
From K7N1636(32/18)49A to K7N1636(32/18)45A.
2. AC parameter change.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20
Final spec release
Release Icc on page 14.
part #
-25
-22
-20
-16
-13
2.1
From
440
400
370
340
280
To
470
430
400
350
290
April 04. 2003
Final
Draft Date
Feb. 23. 2001
May. 10. 2001
Aug. 30. 2001
Dec. 26. 2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
1.0
2.0
May. 10. 2002
May. 22. 2002
Final
Final
1. Delete 119BGA package.
2. Correct the Ball Size of 165 FBGA.
1. Delete x32 Org.
2. Delete the 225MHz speed bin
3.0
Nov. 17, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov. 2003
Rev 3.0
K7N163645A
K7N161845A
512Kx36 & 1Mx18 Pipelined NtRAM
TM
16Mb NtRAM(Flow Through / Pipelined) Ordering Informa
tion
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5 ns
250/200/167/133MHz
250/200/167/133MHz
6.5/7.5 ns
250/200/167/133MHz
250/200/167/133MHz
Q : 100TQFP
F : 165FBGA
PKG
Temp
K7M161825A-QC(I)65/75
1Mx18
K7N161801A-Q(F)C(I)25/20/16/13
K7N161845A-Q(F)C(I)25/20/16/13
K7M163625A-QC(I)65/75
512Kx36 K7N163601A-Q(F)C(I)25/20/16/13
K7N163645A-Q(F)C(I)25/20/16/13
FlowThrough
Pipelined
Pipelined
FlowThrough
Pipelined
Pipelined
3.3
3.3
2.5
3.3
3.3
2.5
C
; Commercial
Temp.Range
I
; Industrial
Temp.Range
-2-
Nov. 2003
Rev 3.0
K7N163645A
K7N161845A
512Kx36 & 1Mx18 Pipelined NtRAM
TM
512Kx36 & 1Mx18-Bit Pipelined NtRAM
TM
FEATURES
• 2.5V
±5%
Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N163645A and K7N161845A are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163645A and K7N161845A are implemented with
SAMSUNG
′s
high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.6
2.6
-20
5.0
3.2
3.2
-16
6.0
3.5
3.5
-13
7.5
4.2
4.2
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
A [0:18]or
A [0:19]
ADDRESS
19
REGISTER
A
2
~A
18
or A
2
~A
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
512Kx36, 1Mx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
36 or 18
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
-3-
Nov. 2003
Rev 3.0
K7N163645A
K7N161845A
PIN CONFIGURATION
(TOP VIEW)
BWb
BWa
512Kx36 & 1Mx18 Pipelined NtRAM
TM
CK E
N.C.
ADV
CS
2
N.C.
CLK
CS
1
CS
2
V
DD
V
SS
WE
A
19
A
18
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
19
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,80,
81,82,83,84,99,100
85
88
89
87
98
97
92
93,94
86
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply
(2.5V)
Ground
No Connect
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BW x(x=a,b)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(2.5V)
Output Ground
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N161845A(1Mx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Note :
A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Nov. 2003
Rev 3.0
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