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AS7C251MFT36A-85TQC

Description
Standard SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
Categorystorage    storage   
File Size521KB,19 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric View All

AS7C251MFT36A-85TQC Overview

Standard SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C251MFT36A-85TQC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time8.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density37748736 bit
Memory IC TypeSTANDARD SRAM
memory width36
Number of functions1
Number of terminals100
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX36
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
January 2005
®
AS7C251MFT32A
AS7C251MFT36A
2.5V 1M
×
32/36 Flow-through synchronous SRAM
Features
Organization: 1,048,576 words × 32 or 36 bits
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow-through operation
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
20
CLK
CE
CLR
Q0
Burst logic
Q1
2
2
D
Q
CE
Address
register
CLK
D
DQ
d
Q
Byte write
registers
CLK
D
DQ
Q
c
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Q
D
1M × 32/36
Memory
array
20
18
20
32/36
32/36
GWE
BWE
BW
d
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
Power
down
D
Enable
Q
delay
register
CLK
32/36
DQ[a:d]
OE
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
8.5
7.5
325
130
90
-85
10
8.5
300
130
90
-10
12
10
275
130
90
Units
ns
ns
mA
mA
mA
1/17/05, v 1.2
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
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