MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100EP222/D
Rev. 2, 09/2001
Low Voltage ECL/PECL
1:15 Clock Driver
The MC100EP222 is a low voltage, low skew 1:15 differential
B1
and
B2
ECL/PECL clock distribution buffer. The MC100EP222 has been
designed and optimized for 2.5 V and 3.3 V systems. Target applications
for this clock driver are high performance clock distribution systems for
computer, networking and telecommunication systems.
Features:
•
15 differential ECL outputs (4 output banks)
•
2 selectable differential ECL inputs
•
Selectable 1:1 or 1:2 frequency outputs
•
Operates from a -2.5, -3.3 V (ECL) or 2.5, 3.3 V (PECL) power supply
•
Extended temperature operating range of -40 to +85 deg C
The MC100EP222 device characteristics allows low-skew clock dis-
tribution of differential and single-ended LVECL/LVPECL signals. Typical
applications for the MC100EP222 are primary clock distribution systems
on backplanes of high-performance computer, networking and telecom-
munication systems.
The MC100EP222 can be operated from a 3.3 V or 2.5 V positive
supply (PECL mode) without the requirement of a negative supply line.
Each of the four output banks of two, three, four and six differential clock
output pairs may be independently configured to distribute the input fre-
quency or
B2
of the input frequency. The FSELA, FSELB, FSELC,
FSELD and CLK_SEL are asychronous control inputs. Any changes of
the control inputs require a MR pulse for resynchronization of the the
B2
outputs. For the functionality of the MR control input, “Timing Diagram” on
page 648.
MC100EP222
See Upgrade Product – MC100ES6222
LOW VOLTAGE 3.3 V/2.5 V
1:15 DIFFERENTIAL ECL/PECL
CLOCK DRIVER
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336
Each of the CLK0, CLK1 inputs can be used differential of single-ended. For single-ended signals, connect the bypassed V
BB
output reference to the unused input of the pair.
The MC100EP222 guarantees low output-to-output skew of 40 (70) ps and device-to-device skew of max. 350 ps. To ensure
low skew clock signals in the application, both sides of any differential output pair need to be terminated identically, even if only
one side is used. When fewer than all fifteen pairs are used, identical termination of all output pairs on the same package side is
recommended. If no outputs on a side are used, it is recommended to leave all of these outputs open and unterminated. This will
maintain minimum output skew.
7
Rev 2
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
647
MC100EP222
FSELA
65 kW
CLK0
65 kW
CLK0
V
CC
65 kW
65 kW
V
EE
B2
B1
QA0
QA1
CLK1
65 kW V
CC
65 kW
QB0
QB1
QB2
CLK1
65 kW
V
EE
CLK_SEL
65 kW
QC0
65 kW
65 kW
QC1
QC2
QC3
MR
FSELB
FSELC
65 kW
QD0
QD1
QD2
7
QD3
FSELD
65 kW
QD4
QD5
VBB
Figure 1. MC100EP222 Logic Diagram
CLK
MR
Q (
B2)
Q (
B1)
Figure 2. MC100EP222 Function Diagram
648
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC100EP222
Figure 3. 52 Lead Package Pinout
(Top View)
VCCO
VCCO
QC0
QC0
QC1
QC1
QC2
QC2
QC3
QC3
NC
NC
28
VCCO
27
VCCO
QB2
QB2
QB1
QB1
QB0
QB0
VCCO
QA1
QA1
QA0
QA0
VCCO
40
41
42
43
44
45
46
47
48
49
50
51
52
39
38
37
36
35
34
33
32
31
30
29
26
25
24
23
22
21
QD0
QD0
QD1
QD1
QD2
QD2
QD3
QD3
QD4
QD4
QD5
QD5
VCCO
MC100EP222
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
FSELA
FSELB
CLK0
CLK0
CLK_SEL
CLK1
CLK1
VCC
VBB
FSELC
Table 1: FUNCTION TABLE
Control Pin
FSELA (asynchronous)
FSELB (asynchronous)
FSELC (asynchronous)
FSELD (asynchronous)
CLK_SEL (asynchronous)
MR (asynchronous)
0
B1
B1
B1
B1
CLK0
Active
1
B2
B2
B2
B2
CLK1
Reset
FSELD
VEE
MR
7
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
649
MC100EP222
Table 2: PIN CONFIGURATION
Pin
CLK0, CLK0
CLK1, CLK1
CLK_SEL
QAn, QAn
QBn, QBn
QCn, QCn
QDn, QDn
FSELA
FSELB
FSELC
FSELD
MR
VBB
VEE
a
V
CC
, V
CCO
a.
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Output
Supply
Supply
I/O
Type
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
Description
Differential reference clock signal input
Alternative differential reference clock signal input
Clock input select
Bank A differential outputs
Bank B differential outputs
Bank C differential outputs
Bank D differential outputs
Selection of bank A output frequency
Selection of bank B output frequency
Selection of bank C output frequency
Selection of bank D output frequency
Reset
DC bias output for single ended input operation
Negative power supply
Positive power supply. All V
CC
and V
CCO
pins must be connected to the
positive power supply for correct DC and AC operation
In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V).
In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V .
In both modes, the input and output levels are referrenced to the most positive supply.
Table 3: ABSOLUTE MAXIMUM RATINGS
a
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
a.
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-65
Characteristics
Min
-0.3
-0.3
-0.3
Max
4.6
V
CC
+0.3
V
CC
+0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
7
Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these con-
ditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated con-
ditions is not implied.
Table 4: GENERAL SPECIFICATIONS
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
θ
JA
θ
JC
a.
b.
Thermal resistance junction to ambient
Thermal resistance junction to case
Characteristics
Output termination voltage
ESD Protection (Machine model)
ESD Protection (Human body model)
ESD Protection (Charged device model
Latch-up immunity
75
1500
500
200
4.0
See application information
b
See application information
Min
Typ
V
CC
- 2
a
Max
Unit
V
V
V
V
mA
pF
Inputs
Condition
Output termination voltage V
TT
= 0V for V
CC
=2.5V operation is supported but the power consumption of the device will increase
Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability prod-
ucts. Thermal package information and exposed pad land pattern design recommendations are available in the applications section of
this datasheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationsship to
long-term reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP222.
650
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC100EP222
Table 5: PECL DC Characteristics
(V
CCO
= V
CC
= 2.375 V to 3.8 V, V
EE
= GND)
Symbol
y
Characteristics
T
A
= -40°C
Min
Max
T
A
= 25°C
Min
Max
T
A
= 85°C
Min
Max
Unit
Condition
Clock input pairs CLK0, CLK0, CLK1, CLK1 (LVPECL differential signals)
V
PP
Differential input
V
CC
=3.3 V
voltage
a
V
CC
=2.5 V
Differential cross point
CLK0,CLK1
voltage
b
Input Current
0.10
0.15
1.0
V
CC
-0.4
150
0.10
0.15
1.0
V
CC
-0.4
150
0.10
0.15
1.0
V
CC
-0.4
150
V
V
V
µA
V
IN
= V
CC
to
V
EE
V
CMR
I
IH
Control inputs (LVPECL single ended)
V
IH
V
IL
I
IH
Input high voltage
Input low voltage
Input Current
V
CC
-1.165
V
CC
-1.810
V
CC
-0.880
V
CC
-1.480
150
V
CC
-1.165 V
CC
-0.880
V
CC
-1.810 V
CC
-1.480
150
V
CC
-1.165
V
CC
-1.810
V
CC
-0.880
V
CC
-1.480
150
V
V
µA
V
IN
= V
CC
to
V
EE
I
OH
= -30mA
c
I
OL
= -5mA
c
LVPECL clock outputs (QAn, QAn, QBn, QBn, QCn, QCn, QDn, QDn)
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
CC
-1.20
V
CC
-1.90
V
CC
-0.82
V
CC
-1.40
V
CC
-1.15
V
CC
-1.90
V
CC
-0.82
V
CC
-1.40
V
CC
-1.15
V
CC
-1.9
V
CC
-0.82
V
CC
-1.40
V
V
Supply current and V
BB
I
EE
I
CC
V
BB
Max. Supply Current
Max. Supply Current
d
Output reference
V
CC
=3.3 V
voltage
e
V
CC
=2.5 V
V
CC
-1.35
V
CC
-1.35
190
675
V
CC
-1.24
V
CC
-1.24
V
CC
-1.35
V
CC
-1.35
190
675
V
CC
-1.24
V
CC
-1.22
V
CC
-1.35
V
CC
-1.35
190
675
V
CC
-1.24
V
CC
-1.22
mA
mA
V
V
V
EE
pin
V
CC
pins
a.
b.
c.
d.
e.
V
PP
is the minimum differential input voltage swing required to maintain device functionality.
V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
Equivalent to an output termination of 50Ω to V
TT
.
I
CC
includes current through the output resistors (all outputs terminated 50W to V
TT
).
V
BB
output can be used to bias the complementary input when the device is used with single ended clock signals. V
BB
can sink max. 0.3
mA DC current.
7
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
651
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