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ALD1102: DescriptionDUAL P-CHANNEL MATCHED MOSFET PAIR; File Size20KB，4 Pages; ManufacturerALD [Advanced Linear Devices]

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ALD1102 Overview

DUAL P-CHANNEL MATCHED MOSFET PAIR

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DVANCED

INEAR

EVICES,

NC.

ALD1102A/ALD1102B

ALD1102

DUAL P-CHANNEL MATCHED MOSFET PAIR

GENERAL DESCRIPTION

The ALD1102 is a monolithic dual P-channel matched transistor pair

intended for a broad range of analog applications. These enhancement-

mode transistors are manufactured with Advanced Linear Devices' en-

hanced ACMOS silicon gate CMOS process.

The ALD1102 offers high input impedance and negative current tempera-

ture coefficient. The transistor pair is matched for minimum offset voltage

and differential thermal response, and it is designed for switching and

amplifying applications in +2V to +12V systems where low input bias

current, low input capacitance and fast switching speed are desired. Since

these are MOSFET devices, they feature very large (almost infinite) current

gain in a low frequency, or near DC operating environment. When used

with an ALD1101, a dual CMOS analog switch can be constructed. In

addition, the ALD1102 is intended as a building block for differential

amplifier input stages, transmission gates, and multiplexer applications.

The ALD1102 is suitable for use in precision applications which require

very high current gain, beta, such as current mirrors and current sources.

The high input impedance and the high DC current gain of the Field Effect

Transistors result in extremely low current loss through the control gate.

The DC current gain is limited by the gate input leakage current, which is

specified at 50pA at room temperature. For example, DC beta of the device

at a drain current of 5mA at 25°C is = 5mA/50pA = 100,000,000.

APPLICATIONS

•

Precision current mirrors

Precision current sources

Analog switches

Choppers

Differential amplifier

input stage

Voltage comparator

Data converters

Sample and Hold

Analog inverter

PIN CONFIGURATION

SOURCE

GATE

DRAIN

TOP VIEW

DA, PA, SA PACKAGE

SUBSTRATE

SOURCE

GATE

DRAIN

FEATURES

•

Low threshold voltage of 0.7V

Low input capacitance

Low Vos grades -- 2mV, 5mV, 10mV

High input impedance -- 10

Ω

typical

Low input and output leakage currents

Negative current (I

) temperature coefficient

Enhancement-mode (normally off)

DC current gain 10

BLOCK DIAGRAM

ORDERING INFORMATION

Operating Temperature Range*

-55°C to +125°C

0°C to +70°C

8-Pin

CERDIP

Package

8-Pin

Plastic Dip

Package

ALD1102A PA

ALD1102B PA

ALD1102 PA

8-Pin

SOIC

Package

DRAIN 1 (3)

GATE 1 (2)

SOURCE 1 (1)

SUBSTRATE (8)

DRAIN 2 (5)

SOURCE 2 (7)

GATE 2 (6)

ALD1102 DA

ALD1102 SA

* Contact factory for industrial temperature range.

ALD1102 Related Products

	ALD1102	ALD1102A	ALD1102BPA	ALD1102DA	ALD1102APA	ALD1102SA	ALD1102B	ALD1102PA
Description	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR	DUAL P-CHANNEL MATCHED MOSFET PAIR
Is it lead-free?	-	-	Contains lead	Contains lead	Contains lead	Contains lead	-	Contains lead
Is it Rohs certified?	-	-	incompatible	incompatible	incompatible	incompatible	-	incompatible
Maker	-	-	ALD [Advanced Linear Devices]	ALD [Advanced Linear Devices]	ALD [Advanced Linear Devices]	ALD [Advanced Linear Devices]	-	ALD [Advanced Linear Devices]
Parts packaging code	-	-	DIP	DIP	DIP	SOT	-	DIP
package instruction	-	-	IN-LINE, R-PDIP-T8	IN-LINE, R-GDIP-T8	IN-LINE, R-PDIP-T8	SMALL OUTLINE, R-PDSO-G8	-	IN-LINE, R-PDIP-T8
Contacts	-	-	8	8	8	8	-	8
Reach Compliance Code	-	-	unknow	unknow	unknow	unknow	-	unknow
ECCN code	-	-	EAR99	EAR99	EAR99	EAR99	-	EAR99
Other features	-	-	LOW THRESHOLD, HIGH INPUT IMPEDANCE	LOW THRESHOLD, HIGH INPUT IMPEDANCE	LOW THRESHOLD, HIGH INPUT IMPEDANCE	LOW THRESHOLD, HIGH INPUT IMPEDANCE	-	LOW THRESHOLD, HIGH INPUT IMPEDANCE
Configuration	-	-	COMMON SUBSTRATE, 2 ELEMENTS	COMMON SUBSTRATE, 2 ELEMENTS	COMMON SUBSTRATE, 2 ELEMENTS	COMMON SUBSTRATE, 2 ELEMENTS	-	COMMON SUBSTRATE, 2 ELEMENTS
Minimum drain-source breakdown voltage	-	-	12 V	12 V	12 V	12 V	-	12 V
Maximum drain-source on-resistance	-	-	270 Ω	270 Ω	270 Ω	270 Ω	-	270 Ω
FET technology	-	-	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	-	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	-	-	R-PDIP-T8	R-GDIP-T8	R-PDIP-T8	R-PDSO-G8	-	R-PDIP-T8
JESD-609 code	-	-	e0	e0	e0	e0	-	e0
Number of components	-	-	2	2	2	2	-	2
Number of terminals	-	-	8	8	8	8	-	8
Operating mode	-	-	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	-	ENHANCEMENT MODE
Maximum operating temperature	-	-	70 °C	125 °C	70 °C	70 °C	-	70 °C
Package body material	-	-	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
Package shape	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	-	-	IN-LINE	IN-LINE	IN-LINE	SMALL OUTLINE	-	IN-LINE
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
Polarity/channel type	-	-	P-CHANNEL	P-CHANNEL	P-CHANNEL	P-CHANNEL	-	P-CHANNEL
Maximum power dissipation(Abs)	-	-	0.5 W	0.5 W	0.5 W	0.5 W	-	0.5 W
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
surface mount	-	-	NO	NO	NO	YES	-	NO
Terminal surface	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	-	-	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	GULL WING	-	THROUGH-HOLE
Terminal location	-	-	DUAL	DUAL	DUAL	DUAL	-	DUAL
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
transistor applications	-	-	SWITCHING	SWITCHING	SWITCHING	SWITCHING	-	SWITCHING
Transistor component materials	-	-	SILICON	SILICON	SILICON	SILICON	-	SILICON

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