EB72F61C08AV2-16.000M
EB72F61 C 08 A V 2 -16.000M
Series
20.2mm x 20.2mm x 10.5mm 3.3V AT-Cut LVCMOS
OCXO
Initial Tolerance
±1.0ppm Maximum
Frequency Stability
±80ppb Maximum
Operating Temperature Range
0°C to +50°C
Nominal Frequency
16.000MHz
Duty Cycle
50% ±5%
Control Voltage
1.65Vdc ±1.65Vdc
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Initial Tolerance
Frequency Stability
Frequency Stability vs. Input Voltage
Frequency Stability vs. Load
Frequency Stability vs. Aging (10
Years)
Frequency Stability vs. Aging (1 Day)
Operating Temperature Range
Supply Voltage
Warm Up Time
Power Consumption
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Control Voltage
Control Voltage Range
Frequency Deviation
Linearity
Reference Voltage Output
Transfer Function
Crystal Cut
Input Impedance
Phase Noise
Storage Temperature Range
16.000MHz
±1.0ppm Maximum (Measured at nominal Vdd and Vc)
±80ppb Maximum
±20ppb Maximum (Vdd ±5%)
±20ppb Maximum (Vload ±5%)
±3.0ppm Maximum (after 72 hours of operation)
±3.0ppb Maximum (after 72 hours of operation)
0°C to +50°C
3.3Vdc ±5%
3 Minutes Maximum (to ±500ppb of final frequency at 1 hour at 25°C)
1.2Watts Maximum at Steady State at 25°C, 3.6Watts Maximum during Warm Up
2.6Vdc Minimum (IOH=-4mA)
0.4Vdc Maximum (IOL=+4mA)
6nSec Maximum (Measured at 20% to 80% of waveform)
50% ±5% (Measured at 50% of waveform)
15pF Maximum
CMOS
1.65Vdc ±1.65Vdc
0.0Vdc to Vdd
±5ppm Minimum (Referenced to Fo at Vc=1.65Vdc; Vcc=3.3Vdc)
±10% Maximum
2.8Vdc ±0.2Vdc (Pin 5)
Positive Transfer Characteristic
AT-Cut
10kOhms Typical
-70dBc/Hz at 1Hz Offset, -95dBc/Hz at 10Hz Offset, -120dBc/Hz at 100Hz Offset, -135dBc/Hz at 1kHz
Offset, -140dBc/Hz at 10kHz Offset (Typical Values)
-55°C to +125°C
Frequency Stability vs. Aging (1 Year)
±500ppb Maximum (after 72 hours of operation)
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Gross Leak Test
Lead Integrity
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2004
MIL-STD-202, Method 213 Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010
MIL-STD-883, Method 2007 Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 1 of 3
EB72F61C08AV2-16.000M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
2
0.6 MAX
3
Ø0.457
±0.100
7.62
±0.10
15.24
±0.20
3
2
1
10.5
±0.5
5.0 ±0.3
20.2
±0.5
5
4
20.2
±0.5
4
5
CONNECTION
Supply Voltage
Output
Case/Ground
Voltage Control
Reference Voltage Output
MARKING
ORIENTATION
LINE MARKING
1
2
3
ECLIPTEK
16.000M
XXYZZ
XX=Ecliptek Manufacturing
Code
Y=Last Digit of the Year
ZZ=Week of the Year
OUTPUT WAVEFORM
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 2 of 3
EB72F61C08AV2-16.000M
Test Circuit for Voltage Control Option
Oscilloscope
Frequency
Counter
Current
Meter
Power
Supply
Voltage
Meter
0.01µF
(Note 1)
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.1µF
(Note 1)
Reference
Voltage
Output
Ground
C
L
(Note 3)
Voltage
Control
Power
Supply
Voltage
Meter
Voltage
Meter
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/16/2010 | Page 3 of 3
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