Rev. 1.01, Dec. 2010
M392B5773CH0
M392B5273CH0
M392B5270CH0
M392B1K70CM0
M392B1K73CM0
240pin VLP Registered DIMM
based on 2Gb C-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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-1-
VLP Registered DIMM
datasheet
Rev. 1.01
DDR3 SDRAM
Table Of Contents
240pin VLP Registered DIMM based on 2Gb C-die
1. DDR3 VLP Registered DIMM Ordering Information ..................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Address Configuration .................................................................................................................................................. 5
4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 6
5. Pin Description ............................................................................................................................................................. 7
6. ON DIMM Thermal Sensor ........................................................................................................................................... 7
7. Input/Output Functional Description.............................................................................................................................. 8
8. Pinout Comparison Based On Module Type................................................................................................................. 9
9. Registering Clock Driver Specification .......................................................................................................................... 10
9.1 Timing & Capacitance values .................................................................................................................................. 10
9.2 Clock driver Characteristics ..................................................................................................................................... 10
10. Function Block Diagram:............................................................................................................................................. 11
10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11
10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 12
10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13
10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14
10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) ..................................................................... 15
11. Absolute Maximum Ratings ........................................................................................................................................ 16
11.1 Absolute Maximum DC Ratings............................................................................................................................. 16
11.2 DRAM Component Operating Temperature Range .............................................................................................. 16
12. AC & DC Operating Conditions................................................................................................................................... 16
12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 16
13. AC & DC Input Measurement Levels .......................................................................................................................... 17
13.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 17
13.2 V
REF
Tolerances.................................................................................................................................................... 18
13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 19
13.3.1. Differential Signals Definition ......................................................................................................................... 19
13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 19
13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 20
13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 21
13.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 21
13.5 Slew rate definition for Differential Input Signals ................................................................................................... 21
14. AC & DC Output Measurement Levels ....................................................................................................................... 22
14.1 Single Ended AC and DC Output Levels............................................................................................................... 22
14.2 Differential AC and DC Output Levels ................................................................................................................... 22
14.3 Single-ended Output Slew Rate ............................................................................................................................ 22
14.4 Differential Output Slew Rate ................................................................................................................................ 23
15. DIMM IDD specification definition ............................................................................................................................... 24
16. IDD SPEC Table ......................................................................................................................................................... 26
17. Input/Output Capacitance ........................................................................................................................................... 29
18. Electrical Characteristics and AC timing ..................................................................................................................... 30
18.1 Refresh Parameters by Device Density................................................................................................................. 30
18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 30
18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 30
18.3.1. Speed Bin Table Notes .................................................................................................................................. 33
19. Timing Parameters by Speed Grade .......................................................................................................................... 34
19.1 Jitter Notes ............................................................................................................................................................ 37
19.2 Timing Parameter Notes........................................................................................................................................ 38
20. Physical Dimensions................................................................................................................................................... 39
20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M392B5773CH0 ............................................................................ 39
20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs ................................................................ 39
-3-
VLP Registered DIMM
datasheet
Rev. 1.01
DDR3 SDRAM
20.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M392B5273CH0 .......................................................................... 40
20.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs .............................................................. 40
20.3 512Mbx4 based 512Mx72 Module (1 Rank) - M392B5270CH0 ............................................................................ 41
20.3.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs ................................................................ 41
20.4 1Gbx4(DDP) based 1Gx72 Module (2 Ranks) - M392B1K70CM0........................................................................ 42
20.4.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs .............................................................. 42
20.4.2. Heat Spreader Design Guide ......................................................................................................................... 43
20.5 512Mbx8(DDP) based 1Gx72 Module (4 Ranks) - M392B1K73CM0 ................................................................... 45
20.5.1. x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs .............................................................. 45
20.5.2. Heat Spreader Design Guide ......................................................................................................................... 46
-4-
VLP Registered DIMM
datasheet
Density
2GB
4GB
4GB
8GB
8GB
Organization
256Mx72
512Mx72
512Mx72
1Gx72
1Gx72
Component Composition
256Mx8(K4B2G0846C-HC##)*9
256Mx8(K4B2G0846C-HC##)*18
512Mx4(K4B2G0446C-HC##)*18
DDP 1Gx4(K4B4G0446C-MC##)*18
DDP 512Mx8(K4B4G0846C-MC##)*18
Rev. 1.01
DDR3 SDRAM
Number of
Rank
1
2
1
2
4
1. DDR3 VLP Registered DIMM Ordering Information
Part Number
2
M392B5773CH0-CF8/H9/K0
M392B5273CH0-CF8/H9/K0
M392B5270CH0-CF8/H9/K0
M392B1K70CM0-CF8/H9/K0
M392B1K73CM0-CF8/H9
Height
18.75mm
18.75mm
18.75mm
18.75mm
18.75mm
NOTE
:
1. "##" - F8/H9/K0
2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
JEDEC standard 1.5V ± 0.075V Power Supply
V
DDQ
= 1.5V ± 0.075V
400MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 6,7,8,9,10,11
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then T
CASE
85°C, 3.9us at 85°C < T
CASE
≤
95°C
Asynchronous Reset
3. Address Configuration
Organization
512Mx4(2Gb) based Module
256Mx8(2Gb) based Module
1Gx4(4Gb DDP) based Module
512Mx8(4Gb DDP) based Module
Row Address
A0-A14
A0-A14
A0-A14
A0-A14
Column Address
A0-A9, A11
A0-A9
A0-A9, A11
A0-A9
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
A10/AP
A10/AP
-5-
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