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P4C1024L-55SCLF

Description
Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 0.445 INCH, LEAD FREE, PLASTIC, SOP-32
Categorystorage    storage   
File Size660KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Environmental Compliance  
Download Datasheet Parametric View All

P4C1024L-55SCLF Overview

Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 0.445 INCH, LEAD FREE, PLASTIC, SOP-32

P4C1024L-55SCLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPyramid Semiconductor Corporation
Parts packaging codeSOIC
package instruction0.445 INCH, LEAD FREE, PLASTIC, SOP-32
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time55 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
JESD-609 codee3
length20.447 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP32,.56
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height2.9972 mm
Maximum standby current0.00003 A
Minimum standby current2 V
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.303 mm
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
V
CC
Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 50µA/50µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE
1,
CE
2
and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
—32-Pin LCC (400x820 mil) [Two-Sided]
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous op-
eration with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and CE
2
high) and output enabling (OE) while write enable (WE)
remains HIGH. By presenting the address under these
conditions, the data in the addressed memory location is
presented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE
1
or OE is
HIGH or WE or CE
2
is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, 600 mil PDIP, or 32-pin LCC package.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10), SOP (S12), LCC (L1)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document #
SRAM125
REV G
Revised September 2010
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