PDM34089SA12TQ datasheet, PDF - EEWORLD Datasheet

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PDM34089SA12TQ: DescriptionStandard SRAM, 64KX32, 12ns, CMOS, PQFP100; Categorystorage storage; File Size292KB，15 Pages; ManufacturerParadigm Technology Inc

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PDM34089SA12TQ Overview

Standard SRAM, 64KX32, 12ns, CMOS, PQFP100

PDM34089SA12TQ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Paradigm Technology Inc
package instruction	QFP, QFP100,.63X.87
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	12 ns
Maximum clock frequency (fCLK)	50 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
memory density	2097152 bit
Memory IC Type	STANDARD SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.003 A
Minimum standby current	3 V
Maximum slew rate	0.21 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED

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PRELIMINARY

PDM34089

3.3V 64K x 32 Fast CMOS

Synchronous Static RAM

with Burst Counter

Features

Description

The PDM34089 is a 2,097,152 bit synchronous ran-

dom access memory organized as 65,536 x 32 bits. It

is designed with burst mode capability and interface

controls to provide high-performance in second

level cache designs for x86, Pentium, 680x0, and

PowerPC microprocessors. Addresses, write data

and all control signals except output enable are con-

trolled through positive edge-triggered registers.

Write cycles are self-timed and are also initiated by

the rising edge of the clock. Controls are provided to

allow burst reads and writes of up to four words in

length. A 2-bit burst address counter controls the

two least-signiﬁcant bits of the address during burst

reads and writes. The burst address counter selec-

tively uses the 2-bit counting scheme required by the

x86 and Pentium or 680x0 and PowerPC micropro-

cessors as controlled by the mode pin. Individual

write strobes provide byte write for the four 8-bit

bytes of data. An asynchronous output enable sim-

pliﬁes interface to high-speed buses.

Interfaces directly with the x86, Pentium™, 680X0

and PowerPC™ processors

Single 3.3V power supply

Mode selectable for interleaved or linear burst:

Interleaved for x86 and Pentium

Linear for 680x0 and PowerPC

Fast access times:

9, 10, 12 and 15 ns

High-density 64K x 32 architecture with burst

address counter

Fully registered inputs

High-output drive: 30 pF at rated T

Asynchronous output enable

Self-timed write cycle

Separate byte write enables and one global write

enable

Internal burst read/write address counter

Internal registers for address, data, controls

Burst mode selectable

Sleep mode

Packages:

100-pin QFP - (Q)

100-pin TQFP - (TQ)

i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.

Rev 1.1 - 5/01/98

PDM34089SA12TQ Related Products

	PDM34089SA12TQ	PDM34089SA10TQTY	PDM34089SA12Q	PDM34089SA12TQTR	PDM34089SA10QTY
Description	Standard SRAM, 64KX32, 12ns, CMOS, PQFP100	Standard SRAM, 64KX32, 10ns, CMOS, PQFP100	Standard SRAM, 64KX32, 12ns, CMOS, PQFP100	Standard SRAM, 64KX32, CMOS, PQFP100	Standard SRAM, 64KX32, 10ns, CMOS, PQFP100
package instruction	QFP, QFP100,.63X.87	QFP,	QFP, QFP100,.7X.9	QFP,	QFP,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknow
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
memory density	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bi
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	32	32	32	32	32
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
word count	65536 words	65536 words	65536 words	65536 words	65536 words
character code	64000	64000	64000	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	64KX32	64KX32	64KX32	64KX32	64KX32
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP	QFP	QFP	QFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.1 V	3.1 V	3.1 V	3.1 V	3.1 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maker	Paradigm Technology Inc	-	Paradigm Technology Inc	Paradigm Technology Inc	Paradigm Technology Inc
Maximum access time	12 ns	10 ns	12 ns	-	10 ns

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