PRELIMINARY
PDM41516
Features
s
High-speed access times
- Com’l: 10, 12, 15, 17 and 20 ns
- Ind: 12, 15, 17 and 20 ns
Low power operation (typical)
- PDM41516SA
Active: 500 mW
Standby: 150 mW
- PDM41516LA
Active: 450 mW
Standby: 100 mW
High-density 32K x 16 architecture
5V (±10%) power supply
Fully static operation
TTL-compatible inputs and outputs
Outbut buffer controls: OE
Data byte controls: LB, UB
Packages:
44-pin Plastic TSOP - T
44-pin Plastic SOJ (400 mil) - SO
32K x 16 CMOS
Static SRAM
Description
The PDM41516 is a high-performance CMOS static
RAM organized as 32,768 x 16 bits. This product is
produced using Paradigm’s proprietary CMOS tech-
nology which offers the designer the highest speed
parts. The PDM41516 features low power dissipa-
tion using chip enable (CE) and has an output
enable input (OE) for fast memory access. Byte
access is supported by upper and lower byte
controls.
The PDM41516 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41516 comes in two versions, a
standard power version PDM41516SA and a low
power version PDM41516LA. The two versions are
functionally the same and only differ in their power
consumption.
The PDM41516 is available in a 400-mil 44-pin plas-
tic SOJ and a 44-pin plastic TSOP package.
1
2
3
4
5
6
7
s
s
s
s
s
s
s
s
Functional Block Diagram
8
9
10
11
12
Rev. 3.0 - 7/17/96
3-49
PRELIMINARY
Pin Configuration
44-Pin TSOP
44-Pin SOJ
Pin Description
Name
A14-A0
I/O15-I/O0
CE
WE
OE
LB, UB
NC
V
CC
V
SS
Description
PDM41516
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
No Connect
Power (+5V)
Ground
Operating Mode
Mode
Read
CE
L
OE
L
WE
H
LB
L
H
L
Write
L
X
L
L
H
L
Output Disable
L
L
Standby
H
H
X
X
H
X
X
X
H
X
UB
L
L
H
L
L
H
X
H
X
I/O7-I/O0
Output
High Impedance
Output
Input
High Impedance
Input
High Impedance
High Impedance
High Impedance
I/O15-I/O8
Output
Output
High Impedance
Input
Input
High Impedance
High Impedance
High Impedance
High Impedance
Power
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
SB
NOTE:1.H = V
IH
, L = V
IL
, X = DON’T CARE
3-50
Rev. 3.0 - 7/17/96
PRELIMINARY
PDM41516
Absolute Maximum Ratings
Symbol
V
TERM
T
BIAS
T
STG
P
D
I
OUT
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
50
Unit
V
°C
°C
W
mA
1
2
3
4
NOTE:1.Stresses greater than those listed under ABSOLUTE MAXIMUM RA
TINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Description
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
4.5
0
0
–40
Typ.
5.0
0
25
25
Max.
5.5
0
70
85
Unit
V
V
°C
°C
5
6
7
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
PSM41516SA
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= Max., V
IN
= Vss to V
CC
V
CC
= Max.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.5
(1)
8
PSM41516LA
Min.
–5
–5
–0.5
(1)
Unit
Max.
5
5
0.8
Vcc +
0.5
0.4
—
Max.
5
5
0.8
Vcc +
0.5
0.4
—
µA
µA
V
V
V
V
9
10
11
12
2.2
—
2.4
2.2
—
2.4
NOTE: 1. V
IL
(min) = –3.0V for pulse width less than 20 ns.
Rev. 3.0 - 7/17/96
3-51
PRELIMINARY
PDM41516
Power Supply Characteristics
-10
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
HC
f=0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
Power
SA
Com’l.
295
-12
-15
-17
-20
Unit
mA
Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind.
285
295
265
275
240
250
220
230
LA
280
270
275
245
265
220
240
200
210
mA
SA
LA
SA
LA
40
30
10
5
40
30
10
5
40
30
15
10
35
25
10
5
35
25
15
10
35
25
10
5
35
25
15
10
30
20
10
5
30
20
15
10
mA
mA
mA
mA
SHADED AREA = ADVANCE INFORMATION
NOTES: All values are maximum guaranteed values.
V
LC
≤
0.2V, V
HC
≥
V
CC
– 0.2V
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= V
SS
V
I/O
= V
SS
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is determined by device characterization, but is not production tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
3 ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
)
3-52
Rev. 3.0 - 7/17/96
PRELIMINARY
PDM41516
Read Cycle Timing Diagram
(2)
1
2
3
4
5
AC Electrical Characteristics
Description
READ Cycle
Symbol
Min
–10
Max
Min
–12
Max
Min
–15
Max
Min
–17
Max
Min
–20
Max
Unit
6
7
8
9
10
11
12
3-53
t
RC
t
AA
t
ACE
t
BA
t
OH
t
LZBE
t
HZBE
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
10
—
—
—
3
0
—
3
—
—
1
—
—
10
10
6
—
—
7
—
6
6
—
6
12
—
—
—
3
0
—
3
—
—
1
—
—
12
12
7
—
—
8
—
7
7
—
7
15
—
—
—
3
0
—
3
—
—
1
—
—
15
15
8
—
—
9
—
8
8
—
8
17
—
—
—
3
0
—
3
—
—
1
—
—
17
17
9
—
—
9
—
9
9
—
9
20
—
—
—
3
0
—
3
—
—
1
—
—
20
20
9
—
—
7
—
9
9
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ cycle time
Address access time
Chip enable access time
Byte access time
Output hold from address change
Byte disable to output in low-Z
Byte enable to output in high-Z
Chip enable to output in low-Z
(1)
Chip disable to output high-Z
(1, 2)
Output enable access time
Output enable to output in low-Z
Output disable to output in high-Z
(2)
SHADED AREA = ADVANCE INFORMATION
NOTES: 1. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
.
2. t
HZCE
, t
HZOE
, and t
HZWE
are specified with C
L
= 5 pF as in Figure 2. Transition is measured ± 200 mV from
steady state voltage.
Rev. 3.0 - 7/17/96
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