8M x 64 (72) Synchronous DRAM
PUMA 64SDVA512X
Issue 5.0 December 1999
Description
The PUMA64SDVA512X is a cost effective,
unbuffered synchronous DRAM ECC Memory
component organised as 8M x 64 (or 72). It uses ten
4M x 16 SDRAM devices in a 160 pin Plastic Quad
Flat Pack (PQFP) package to achieve up to twice the
density of existing standard solutions. The device is
designed to be soldered direct to the PCB,
eliminating all socket reliability problems.
PC-100 compatible variants are available which can
sustain data transfer rates up to 100MHz. 66MHz
variants are also available. All control, data and
address input circuits are sampled on the positive
edge of the system clock for fully synchronous
operation.
A 256byte EEPROM is used to implement serial
presence detect capability on board the module. The
lower 128 bytes is reserved for module configurations
programmed by the factory. The upper 128bytes are
available for customer use.
Block Diagram
10
Ω
CLK2
CKE1
/CS1
CKE0
/CS0
/RAS
/CAS
/WE
A(11:0), BA0~1
D(15:0)
DQM0
DQM1
CLK0
10pf
15pf
Vdd
10k
SCL
SDA
10
Ω
4M x 16
SDRAM
4M x 16
SDRAM
SA
0
SA
1
SA
2
SPD
EEPROM
10
Ω
WP
47k
10
Ω
D(47:32)
DQM4
DQM5
4M x 16
SDRAM
4M x 16
SDRAM
10
Ω
CB(7:0)
4M x 16
SDRAM
4M x 16
SDRAM
/CS3
/CS2
CLK3
10
Ω
15pf
10
Ω
D(31:16)
DQM2
DQM3
10
Ω
CLK1
10pf
4M x 16
SDRAM
4M x 16
SDRAM
Features
• Unbuffered synchronous DRAM module organised
as 2 banks of 4Mx64 (or 72)
• 3.3V + 0.3V power supply.
• Commercial and Industrial temperature grades
• Space saving 28mm square 160pin PQFP package
(0.65mm pin pitch).
• PC 100 compatible operation.
10
Ω
D(63:48)
DQM6
DQM7
4M x 16
SDRAM
4M x 16
SDRAM
Pin Functions
Description
Address Input
Select Bank
Data I/O
Clock Input
Clock Enable Input
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data I/O Mask
Power
Ground
Serial Data I/O
Serial Clock
Address in EEPROM
Write Protection
Check Bits
Do Not Use
No Connection
Signal
A0~A11
BA0~BA1
D0~D63
CLK0~CLK3
CKE0~CKE1
/CS0~3
/RAS
/CAS
/WE
DQM~7
VDD
VSS
SDA
SCL
SA0~2
WP
CB0~7
DNU
NC
•
4 internal SDRAM banks
•
Fully synchronous operation to rising edge of sys-
tem clock.
•
Auto refresh and self refresh modes (4K/64ms)
•
Sequential and interleved burst mode operation
•
Programmable burst length (1,2,4,8,Full page)
•
Serial presence detect EEPROM
•
On board decoupling capacitors
Package Details
PUMA 64 - Plastic 160pin PQFP package
Max. Dimensions - 31.35 x 31.35 x 5.02
Max. over pins
All dimensions in mm.
11403 West Bernardo Court, Suite 100, San Diego, CA92127.
TEL (001) 858 674 2233, Fax No. (001) 858 674 2230 E-mail:
sales@mosaicsemi.com
Ordering Information
Ordering Information
PUMA 64SDVA512I T1X
X = Pinout Variant
Type
Temp. Range
Density (MBit)
Voltage
Technology
Package
Refer to table below
Blank = Commercial
I = Industrial
512 = 512MBit
VA = 3.3V
SD = Synchronous DRAM
PUMA 64 = 160 Pin PQFP
Type
T1
T2
T3
T4
ECC
8 Bit
8 Bit
No
No
Refresh
4K
4K
4K
4K
PC100 Compatible
Yes
Yes
Yes
Yes
Speed
Registered/Buffered
No
Yes
No
Yes
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
PAGE 4
http://www.mosaicsemi.com/
Issue 5.0 December 1999
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