S29GL512N
S29GL256N
S29GL128N
512, 256, 128 Mbit, 3 V, Page Flash
Featuring 110 nm MirrorBit
This product family has been retired and is not recommended for designs. For new and current designs, S29GL128S, S29GL256S,
and S29GL512T supersede the S29GL128N, S29GL256N, and S29GL512N respectively. These are the factory-recommended
migration paths. Please refer to the S29GL-S and S29GL-T Family data sheets for specifications and ordering information.
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– 3 volt read, erase, and program operations
Enhanced VersatileI/O Control
– All input levels (address, control, and DQ input levels) and outputs
are determined by voltage on V
IO
input. V
IO
range is 1.65 to V
CC
Manufactured on 110 nm MirrorBit Process Technology
Secured Silicon Sector Region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence
– May be programmed and locked at the factory or by the customer
Flexible Sector Architecture
– S29GL512N: Five hundred twelve 64 Kword (128 Kbyte) sectors
– S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors
– S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte)
sectors
Compatibility with JEDEC Standards
– Provides pinout and software compatibility for single-power supply
flash, and superior inadvertent write protection
20-year Data Retention typical
Package Options
– 56-pin TSOP
– 64-ball Fortified BGA
Software & Hardware Features
Software Features
– Program Suspend and Resume: read other sectors before
programming operation is completed
– Erase Suspend and Resume: read/program other sectors before
an erase operation is completed
– Data# polling and toggle bits provide status
– Unlock Bypass Program command reduces overall multiple-word
programming time
– CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
Hardware Features
– Advanced Sector Protection
– WP#/ACC input accelerates programming time (when high
voltage is applied) for greater throughput during system
production. Protects first or last sector regardless of sector
protection settings
– Hardware reset input (RESET#) resets device
– Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
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Performance Characteristics
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100,000 Erase Cycles per sector typical
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Low Power Consumption (typical values at 3.0 V, 5 MHz)
– 25 mA typical active read current;
– 50 mA typical erase/program current
– 1 µA typical standby mode current
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High Performance
– 90 ns access time (S29GL128N, S29GL256N)
– 100 ns (S29GL512N)
– 8-word/16-byte page read buffer
– 25 ns page read times
– 16-word/32-byte write buffer reduces overall programming time for
multiple-word updates
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Density
512 Mb
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Product Availability Table
Init. Access
110 ns
100 ns
110 ns
256 Mb
100 ns
90 ns
110 ns
128 Mb
100 ns
90 ns
V
CC
Full
Full
Full
Full
Regulated
Full
Full
Regulated
Availability
Now
Now
Now
Now
Now
Now
Now
Now
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Cypress Semiconductor Corporation
Document Number: 002-01522 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 08, 2016
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S29GL512N
S29GL256N
S29GL128N
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nmMirrorBit technology.
The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as
16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The
devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N), 100 ns (S29GL512N) are available. Note that each access time has a
specific operating voltage range (V
CC
) and an I/O voltage range (V
IO
), as specified in the
Product Selector Guide
on page 4
and the
Ordering Information
on page 9.
The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power supply
for both read and write functions. In addition to a V
CC
input, a high-
voltage
accelerated program (WP#/ACC)
input provides shorter programming times through increased current. This feature is
intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are written to
the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the
programming and erase operations.
Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the
host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or monitor the
Ready/Busy# (RY/BY#)
output to
determine whether the operation is complete. To facilitate programming, an
Unlock Bypass
mode reduces command sequence
overhead by requiring only two write cycles to program data instead of four.
The
Enhanced VersatileI/O™
(V
IO
) control allows the host system to set the voltage levels that the device generates and tolerates
on all input levels (address, chip control, and DQ input levels) to the same voltage level that is asserted on the V
IO
pin. This allows
the device to operate in a 1.8 V or 3 V system environment as required.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions.
Persistent Sector Protection
provides in-system, command-enabled protection of any combination of sectors using a
single power supply at V
CC
.
Password Sector Protection
prevents unauthorized write and erase operations in any combination of
sectors through a user-defined 64-bit password.
The
Erase Suspend/Erase Resume
feature allows the host system to pause an erase operation in a given sector to read or
program any other sector and then complete the erase operation. The
Program Suspend/Program Resume
feature enables the
host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation in progress and resets the device, after which it is then ready for a new
operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the
host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels on CE# and RESET#, or when
addresses have been stable for a specified period of time.
The
Secured Silicon Sector
provides a 128-word/256-byte area for code or data that can be permanently protected. Once this
sector is protected, no further changes within the sector can occur.
The
Write Protect (WP#/ACC)
feature protects the first or last sector by asserting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase.
The data is programmed using hot electron injection.
Document Number: 002-01522 Rev. *B
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The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
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Page 2 of 92
S29GL512N
S29GL256N
S29GL128N
Contents
1.
1.1
1.2
2.
3.
3.1
4.
5.
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
8.
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
Product Selector Guide
............................................... 4
S29GL512N ................................................................... 4
S29GL256N, S29GL128N ............................................. 4
Block Diagram..............................................................
5
Connection Diagrams..................................................
6
Special Package Handling Instructions.......................... 7
Pin Description.............................................................
7
Logic Symbol
............................................................... 7
Ordering Information
................................................... 9
Device Bus Operations..............................................
Word/Byte Configuration..............................................
VersatileIO
TM
(V
IO
) Control ..........................................
Requirements for Reading Array Data.........................
Writing Commands/Command Sequences..................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Autoselect Mode ..........................................................
Sector Protection .........................................................
Advanced Sector Protection ........................................
Lock Register ...............................................................
Persistent Sector Protection ........................................
Persistent Protection Mode Lock Bit ............................
Password Sector Protection.........................................
Password and Password Protection Mode Lock Bit ....
64-bit Password ...........................................................
Persistent Protection Bit Lock (PPB Lock Bit)..............
Secured Silicon Sector Flash Memory Region ............
Write Protect (WP#) .....................................................
Hardware Data Protection............................................
10
10
10
10
11
11
12
12
13
34
34
35
35
36
37
38
38
38
38
39
40
40
43
43
43
44
44
44
48
49
50
51
51
52
52
53
53
Page 3 of 92
9.15 Secured Silicon Sector Entry Command....................... 54
9.16 Secured Silicon Sector Exit Command ......................... 54
9.17 Command Definitions.................................................... 54
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11.
12.
Write Operation Status
............................................... 59
DQ7: Data# Polling ....................................................... 59
RY/BY#: Ready/Busy#.................................................. 60
DQ6: Toggle Bit I .......................................................... 60
DQ2: Toggle Bit II ......................................................... 62
Reading Toggle Bits DQ6/DQ2..................................... 62
DQ5: Exceeded Timing Limits ...................................... 62
DQ3: Sector Erase Timer.............................................. 63
DQ1: Write-to-Buffer Abort............................................ 63
Absolute Maximum Ratings.......................................
64
Operating Ranges
....................................................... 65
13. DC Characteristics......................................................
65
13.1 CMOS Compatible ........................................................ 65
14. Test Conditions
........................................................... 66
14.1 Key to Switching Waveforms ........................................ 67
15.
15.1
15.2
15.3
15.4
16.
17.
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Common Flash Memory Interface (CFI)
................... 40
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence........................................
Word Program Command Sequence...........................
Program Suspend/Program Resume Command
Sequence.....................................................................
Chip Erase Command Sequence ................................
Sector Erase Command Sequence .............................
Erase Suspend/Erase Resume Commands ................
Lock Register Command Set Definitions .....................
Password Protection Command Set Definitions ..........
Non-Volatile Sector Protection Command Set
Definitions ....................................................................
Global Volatile Sector Protection Freeze Command
Set...............................................................................
Volatile Sector Protection Command Set.....................
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Document Number: 002-01522 Rev. *B
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18. Physical Dimensions
.................................................. 78
18.1 TS056—56-Pin Standard Thin Small Outline Package
(TSOP).......................................................................... 78
18.2 LAA064—64-Ball Fortified Ball Grid Array (FBGA)....... 79
19. Advance Information on S29GL-P Hardware Reset
(RESET#) and Power-up Sequence
................................... 80
20. Advance Information on S29GL-R 65 nm MirrorBit .....
Hardware Reset (RESET#) and Power-up Sequence
....... 82
Document History Page
............................................. 84
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AC Characteristics......................................................
68
Read-Only Operations .................................................. 68
Hardware Reset (RESET#)........................................... 69
Erase and Program Operations .................................... 71
Alternate CE# Controlled Erase and Program Operations:
S29GL128N, S29GL256N, S29GL512N....................... 75
Erase And Programming Performance.....................
77
TSOP Pin and BGA Package Capacitance................
77
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S29GL512N
S29GL256N
S29GL128N
1.
1.1
Product Selector Guide
S29GL512N
Part Number
S29GL512N
V
CC
= 2.7–3.6 V
V
IO
= 2.7–3.6 V
V
IO
= 1.65–3.6 V
100
100
25
25
110
110
25
35
10
11
11
110
110
30
35
Speed Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
1.2
S29GL256N, S29GL128N
Part Number
V
CC
= 2.7–3.6 V
V
CC
= Regulated (3.0–3.6 V)
V
IO
= 2.7–3.6 V
V
IO
= 1.65–3.6 V
V
IO
= Regulated (3.0–3.6 V)
S29GL256N, S29GL128N
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10
11
11
100
100
25
25
110
110
25
35
110
110
30
35
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
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Max. Access Time (ns)
Document Number: 002-01522 Rev. *B
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Speed Option
90
90
90
25
25
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Page 4 of 92
S29GL512N
S29GL256N
S29GL128N
2. Block Diagram
RY/BY#
V
CC
V
SS
V
IO
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ15
–
DQ0 (A-1)
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
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Data
Latch
OE#
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Y-Decoder
D
Y-Gating
Cell Matrix
CE#
de
Timer
Address Latch
V
CC
Detector
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STB
A
Max
**–A0
Document Number: 002-01522 Rev. *B
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Note
** A
Max
GL512N = A24, A
Max
GL256N = A23, A
Max
GL128N = A22
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X-Decoder
Page 5 of 92
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