PI6CV857B
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
• Operating Frequency up to 200 MHz and exceeds PC2700
RDIMM specification
• Distributes one differential clock input pair to ten differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
• Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
• Available Packages: 48-pin TSSOP, and 40-pin QFN
Product Description
PI6CV857B PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 V
DDQ
and 2.5V
AV
DD
operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9],
Y[0:9]) and one differential pair feedback clock outputs
(FBOUT,FBOUT) . The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AV
DD
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AV
DD
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857B clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CV857B is also able to track Spread Spectrum Clocking for
reduced EMI.
Block Diagram
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
CLK
CLK
FBIN
FBIN
PLL
PWRDWN
AVDD
Powerdown
and Test
Logic
1
PS8639A
03/21/03
V
DDQ
Y5
V
DDQ
Y6
Y1
Y1
Y0
GND
Y2
Y2
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
1
2
3
4
5
6
7
8
9
40 39 38 37 36 35 34 33 32 31
Y0
Y5
Y6
Y9
V
DDQ
Y3
V
DDQ
Y3
Y4
Y4
Y9
Y8
Y8
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Pin Configurations
48-pin TSSOP (package code A)
40-pin QFN (package code ZD)
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CLK
CLK
VD D Q
AV D D
AG N D
GND
Y3
Y3
VD D Q
Y4
Y4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
P W R DW N
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
30
29
28
27
26
25
24
23
22
Y7
Y7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
V
DDQ
FBOUT
FBOUT
GND
21
10
11 12 13 14 15 16 17 18 19 20
2
PS8639A
03/21/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Pinout Table
Pin Name
CLK
CLK
Yx
Yx
FBOUT
FBOUT
FBIN
FBIN
Pin No.
13
14
3,5,10,20,22,27,29,39,44,46
2,6,9,19,23,26,30,40,43,47
32
33
36
35
I
PWRDWN
37
O
I/O Type
I
Reference Clock input
Clock outputs.
Complement Clock outputs.
Feedback output, and Complement Feedback Output
Feedback Input, and Complement Feedback Input
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,
the part is powered down and the differential clock outputs are disabled to a
3- state. When PWRDWN = 1, all differential clock outputs are enabled and run
at the same frequency as CLK.
Power Supply for I/O.
Power
Analog /core power supply. AV
DD
can be used to bypass the PLL for testing
purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
De s cription
V
DDQ
AV
DD
AGND
GND
4,11,12,15,21,28,34,38,45
16
17
1,7,8,18,24,25,31,41,42,48
Ground
Function Table
Inputs
AV
DD
GND
GND
X
X
2.5V(nom)
2.5V(nom)
2.5V(nom)
PWRDWN
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
<20 MHz
(1)
CLK
H
L
H
L
H
L
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
Outputs
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
Bypassed/off
Bypassed/off
off
off
on
on
off
PLL
Notes:
For testing and power saving purposes, PI6CV857B will power down if the frequency of the reference inputs CLK, CLK is
well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857B will
be powered down when the CLK,CLK stop running.
Z = High impedance
X = Don’t care
3
PS8639A
03/21/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DDQ
, AV
DD
V
I
V
O
I
IK
I
OK
I
O
I
O(PWR)
Tstg
Parame te r
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Output voltage range
Input Clamp Current
Output Clamp Current
Continuous output Current
Continuous current through each V
DD
, V
DDQ
, or GND
Storage temperature
M in.
– 0.5
– 0.5
– 0.5
– 50
– 50
– 50
– 100
– 65
M a x.
3.6
V
DDQ
+0.5
50
50
50
10 0
150
o
Units
V
mA
C
Note:
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Specifications
Recommended Operating Conditions
Symbol
AV
DD
V
DDQ
V
IL
V
IH
V
I
I
OH
I
OL
V
IX
V
IN
V
ID
V
OD
T
A
Parame te r
Analog/core supply voltage
Output supply voltage
Low- level input voltage for PWRDWN pin
High- level input voltage for PWRDWN pin
Input Voltage
High- level output current
Low- level output current
Input differential- pair crossing voltage
Input voltage level
Input differential voltage between CLK and CLK
Output differential voltage between Y[n] &Y[n] and
FBOUT & FBOUT
Operating free air temperature
M in.
2.3
2.3
–0.3
1.7
0
–
–
(V
DDQ
/2) –0.2
–0.3
0.36
0.7
–40
Nom.
2.5
2.5
M ax.
2.7
2.7
0.7
V
DDQ
+0.3
V
DDQ
12
–12
(V
DDQ
/2) +0.2
V
DDQ
+0.3
V
DDQ
+0.6
V
DDQ
+0.6
85
°C
V
mA
V
Units
4
PS8639A
03/21/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Timing Requirements
(Over recommended operating free-air temperature)
Symbol
De s cription
Operating clock frequency
(1,2)
Application clock frequency
(3)
Input clock duty cycle
PLL stabilization time after powerup
AV
DD
, V
DDQ
= 2.5V ±0.2V
M in.
60
95
40
M a x.
200
200
60
100
Units
f
CK
t
DC
t
STAB
MHz
%
µs
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the
other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics (Over recomended operating free-air temperature)
Parame te r
V
IK
V
O H
V
O L
I
I
All inputs
High output voltage
Low output voltage
CLK, FBIN
PWRDWN
I
DDQ
Dynamic supply current of V
DDQ
Static supply current
Dynamic supply current of AV
DD
I
ADD
Static supply current
CLK and CLK
FBIN and FBIN
CLK and CLK
FBIN and FBIN
Part to Part input Capacitance
Variation
(5)
Te s t Conditions
I
I
= –18mA
I
O H
= –100µA
I
O H
= –12mA
I
O L
= 100µA
I
O L
= 12mA
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
V
DD
= 2.7V
CLK & CLK <20 MHz or
PWRDWN = Low
(4)
V
DD
= 2.7V
CLK & CLK <20 MHz or
PWRDWN = Low
(4)
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
2.5V
2.5V
2.5V
2.0
–0 . 2 5
2.7V
A
VD D
, V
D D Q
2.3V
2.3 to 2.7V
2.3V
2.3 to 2.7V
2.3V
VDDQ– 0.1
1.7
0.1
0.6
±10
300
10 0
12
10 0
3.5
0.25
1
pF
µA
mA
µA
mA
µA
V
M in.
Typ.
M ax.
–1.2
Units
C
I
C
I (
∆ )
∆C
I
Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
5
PS8639A
03/21/03
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