MM745HC174 — Hex D-Type Flip-Flops with Clear
January 2009
MM74HC174 — Hex D-Type Flip-Flops with Clear
Features
Typical Propagation Delay: 16ns
Wide Operating Voltage Range: 2V–6V
Low Input Current: 1µA maximum
Low Quiescent Current: 80µA (74HC Series)
Output Drive: 10 LSTTL Loads
Description
The MM74HC174 edge-triggered flip-flops utilize
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low-power,
and speeds comparable to low-power Schottky TTL
circuits. This device contains six master-slave flip-flops
with a common clock and common clear. Data on the D
input with the specified setup and hold times is
transferred to the Q output on the LOW-to-HIGH
transition of the CLOCK input. When LOW, the input
sets all outputs to a LOW state.
Each output can drive ten low-power Schottky TTL
equivalent loads. The MM74HC174 is functionally and
pin comparable to the 74LS174. All inputs are protected
from damage due to static discharge by diodes to V
CC
and ground.
Ordering Information
Part Number
MM74HC174M
MM74HC174MX
MM74HC174MTC
MM74HC174MTCX
MM74HC174N
Operating
Temperature
Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
Eco Status
Package
Packing
Method
Tubes
Tape and
Reel
Tubes
Tape and
Reel
Tubes
RoHS
16-Lead Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150 Inch Narrow
16-Lead Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package
(PDIP), JEDEC MS-001, 0.300 Inch Wide
RoHS
RoHS
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
© 1999 Fairchild Semiconductor Corporation
MM74HC174 • Rev. 1.1.0
www.fairchildsemi.com
MM74HC174 — Hex D-Type Flip-Flop with Clear
Pin Configuration
Figure 1. Pin Configuration (Top View)
Truth Table
(Each Flip-Flop)
Inputs
Clear
LOW
HIGH
HIGH
HIGH
Logic Diagram
Output
D
Q
LOW
HIGH
LOW
Q
0
(2)
Clock
Don’t Care
↑
↑
(1)
(1)
Don’t Care
HIGH
LOW
Don’t Care
LOW
Notes:
1. Transition from LOW to HIGH level.
2. The level of Q before the indicated steady-state
input conditions were established.
Figure 2. Logic Diagram
© 1999 Fairchild Semiconductor Corporation
MM74HC174 • Rev. 1.1.0
www.fairchildsemi.com
2
MM74HC174 — Hex D-Type Flip-Flop with Clear
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. Unless otherwise noted, all voltages are referenced
to ground.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
T
L
Supply Voltage
DC Input Voltage
Parameter
Min.
-0.5
-1.5 to V
CC
-0.5 to V
CC
Max.
+7.0
+1.5
+0.5
±20
±25
±50
Unit
V
V
V
mA
mA
mA
°C
mW
°C
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
DC V
CC
or GND Current, per Pin
Storage Temperature Range
Power Dissipation
(3)
-65
+150
600
500
260
TSSOP, PDIP
SOIC
Lead Temperature, Soldering10 Seconds
Notes:
3. Power dissipation temperature derating— plastic “N” package:12mW/°C from 65° to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
Conditions
Min.
2
0
-40
Max.
6
V
CC
+85
1000
500
400
Unit
V
V
°C
ns
ns
ns
V
CC
=2.0V
Input Rise and Fall Times
V
CC
=4.5V
V
CC
=6.0V
© 1999 Fairchild Semiconductor Corporation
MM74HC174 • Rev. 1.1.0
www.fairchildsemi.com
3
MM74HC174 — Hex D-Type Flip-Flop with Clear
DC Electrical Characteristics
(4)
V
CC
(V)
2.0
V
IH
Minimum HIGH Level Input
4.5
6.0
2.0
V
IL
Minimum LOW Level Input
4.5
6.0
2.0
V
IN
=V
IH
or
V
IL
,⏐I
OUT
⏐≤
20µA
V
OH
Minimum HIGH Level Output
V
IN
=V
IH
or
Voltage
V
IL
,⏐I
OUT
⏐≤
4.0mA
V
IN
=V
IH
or
V
IL
,⏐I
OUT
⏐≤
5.2mA
V
IN
=V
IH
or
V
IL
,⏐I
OUT
⏐≤
20µA
V
OL
Minimum LOW Level Output
V
IN
=V
IH
or
Voltage
V
IL
,⏐I
OUT
⏐≤
4.0mA
V
IN
=V
IH
or
V
IL
,⏐I
OUT
⏐≤
5.2mA
I
IN
I
CC
Maximum Input Current
V
IN
=V
CC
or GND
Maximum Quiescent Supply V
IN
=V
CC
or GND,
Current
I
OUT
=0µA
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
2.0
4.5
6.0
4.20
5.70
0
0
0
00.2
0.20
T
A
=25°C
T
A
=-40
to+85°C
T
A
=-55
to
+125°C
Symbol
Parameter
Conditions
Units
Typ.
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
V
3.70
5.20
0.1
0.1
0.1
V
0.40
0.40
±1.0
160
µA
µA
V
V
Note:
4. For a power supply of 5V ±10%, the worst-case output voltages (V
OH
and V
OL
) occur for HC at 4.5V. The 4.5V
values should be used when designing with this supply. Worst-case V
IH
and V
IL
occur at V
CC
= 5.5V and 4.5V,
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst-case leakage current (I
IN
, I
CC
, and I
OZ
) occurs for CMOS
at the higher voltage, so the 6.0V values should be used.
© 1999 Fairchild Semiconductor Corporation
MM74HC174 • Rev. 1.1.0
www.fairchildsemi.com
4
MM74HC174 — Hex D-Type Flip-Flops with Clear
AC Electrical Characteristics
V
CC
= 5V, T
A
= 25°C and C
L
= 15pF, t
r
= t
f
= 6ns.
Symbol
f
MAX
t
PHL
,t
PLH
t
REM
t
S
t
H
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation Delay, Clock, or Clear to Output
Minimum Removal Time, Clear to Clock
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
Minimum Pulsewidth, Clock or Clear
(5)
Typ.
50
16
-2
10
0
10
Guaranteed Limit
30
30
5
20
5
16
Unit
MHz
ns
ns
ns
ns
ns
AC Electrical Characteristics
C
L
= 50pF, t
r
= t
f
= 6ns unless otherwise noted.
Symbol
Parameter
V
CC
(V)
2.0
T
A
=25°C
Typ.
5
27
31
55
18
16
1
1
1
42
12
10
1
1
1
35
10
8
30
8
7
165
33
28
5
5
5
100
20
17
5
5
5
80
16
14
75
15
13
1000
500
400
136
5
10
T
A
=-40
to+85°C
T
A
=-55 to
+125°C Units
3
18
20
248
49
42
5
5
5
150
30
25
5
5
5
120
24
20
110
22
19
1000
500
400
pF
ns
ns
ns
ns
ns
ns
ns
MHz
Guaranteed Limits
4
21
24
206
41
35
5
5
5
125
25
21
5
5
5
106
20
18
95
19
16
1000
500
400
f
MAX
Maximum Operating Frequency
4.5
6.0
2.0
t
PHL
,t
PLH
Maximum Propagation Delay, Clock,
or Clear to Output
4.5
6.0
2.0
t
REM
Minimum Setup Time, Data to Clock
4.5
6.0
2.0
t
S
Minimum Setup Time, Data to Clock
4.5
6.0
2.0
t
H
Minimum Hold Time, Clock to Data
4.5
6.0
2.0
t
W
Minimum Pulse Width, Clock or Clear
4.5
6.0
2.0
t
TLH
,t
THL
Maximum Output Rise and Fall Time
4.5
6.0
2.0
t
r
,t
f
Maximum Input Rise and Fall Time
Power Dissipation Capacitance
(per Package)
Maximum Input Capacitance
(5)
4.5
6.0
C
PD
C
IN
10
10
pF
Note:
2
5. C
PD
determines the no-load dynamic power consumption, P
D
= C
PD
V
CC
f + I
CC
V
CC
, and the no-load dynamic
current consumption, I
S
= C
PD
V
CC
f + I
CC
.
© 1999 Fairchild Semiconductor Corporation
MM74HC174 • Rev. 1.1.0
www.fairchildsemi.com
5
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