21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2405
Zero-Delay Clock Buffer
Product Features
•
•
•
•
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 300ps
Internal feedback allows outputs to be synchronized
to the clock input
•
5V tolerant input*
•
Operates at 3.3V V
DD
•
Space-saving Packages:
150-mil SOIC (W)
173-mil TSSOP (L)
* CLKIN must reference the same voltage thresholds for the
PLL to deliver zero delay skewing
Functional Description
The PI6C2405 is a PLL based, zero-delay buffer, with the ability
to distribute five outputs of up to 133MHz at 3.3V. All the outputs
are distributed from a single clock input CLKIN and output OUT0
performs zero delay by connecting a feedback to PLL.
An internal feedback on OUT0 is used to synchronize the outputs
to the input; the relationship between loading of this signal
and the outputs determines the input-output delay.
PI6C2405 is characterized for both commercial and industrial opera-
tion
Block Diagram: PI6C2405
Pin Configuration: PI6C2405
CLKIN
1
2
3
4
8
OUT0
OUT4
V
DD
OUT3
CLKIN
PLL
OUT0
OUT1
OUT2
OUT3
OUT2
OUT1
GND
8-Pin
W, L
7
6
5
PI6C2405(–1, –1H)
OUT4
Pin Description for PI6C2405
Pin
1
2, 3, 5, 7
4
6
8
Signal
C LK IN
O UT[1- 4]
GN D
V
DD
O UT0
C lock outputs,
3.3V supply
Ground
C lock output, internal PLL feedback (weak pull- down)
D e s cription
Input clock reference frequency (weak pull- down)
1
PS8592
01/14/02
CLKIN - Input to OUTx Delay (ps)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2405
Zero Delay Clock Buffer
Zero Delay and Skew Control
800
600
400
200
0
-200
-400
-600
-800
-900
-25
-20
CLKIN Input to OUTx Delay vs. Difference in Loading between OUT0 pin and OUTx pins
-15
-10
-5
0
5
10
15
20
25
PI6C2405-1H
PI6C2409-1H
PI6C2409-1
PI6C2405-1
Output Load Difference: OUT0 Load - OUTx Load (pF)
-1000
The relationship between loading of the OUT0 signal and other outputs determines the input-output delay. Zero delay is achieved when
all outputs, including feedback, are loaded equally.
Maximum Ratings
Supply Voltage to Ground Potential ............................................................................................................................. 0.5V to +7.0V
DC Input Voltage (Except CLKIN) ........................................................................................................................ 0.5V to V
DD
+0.5V
DC Input Voltage CLKIN ...................................................................................................................................................... 0.5 to 7V
Storage Temperature ................................................................................................................................................... 65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC
Junction Temperature .................................................................................................................................................................. 150ºC
Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V
Operating Conditions
(V
CC
= 3.3V ±0.3V)
Parame te r
V
DD
T
A
C
L
C
IN
Supply Voltage
Commerical Operating Temperature
Industrial Operating Temperature
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
De s cription
M in.
3.0
0
40
M ax.
3.6
70
85
30
15
7
pF
Units
V
ºC
¾
¾
¾
2
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01/14/02
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PI6C2405
Zero Delay Clock Buffer
DC Electrical Characteristics for Industrial Temperature Devices
Parame te r
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PI6C2309)
I
DD
D e s cription
Input LO W Voltage
Input HIGH Voltage
Input LO W Current
Input HIGH Current
O utput LO W Voltage
O utput HIGH Voltage
Bypass, PLL O FF
Supply Current
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (1); I
OL
= 12mA (1H)
I
OH
= 8mA (1); I
OH
= 12mA (1H)
SEL1 = 0, SEL2 = 1
Unloaded outputs 100 MHz, Select inputs at V
DD
or GND
Unloaded outputs 66 MHz, CLK IN
2.4
25.0
54.0
39.0
2.0
50.0
100.0
0.4
Te s t Conditions
M in.
M ax.
0.8
Units
V
m
A
V
m
A
mA
AC Electrical Characteristics for Industrial Temperature Devices
Parame te rs
F
O
t
DC
N ame
O utput Frequency
Duty C ycle
(1)
(1 )
Duty C ycle
(1)
(1H)
t
R
Rise Time
(1)
(1)
Rise Time
(1)
(1H)
t
F
Fall
Time
(1)
(1)
20pF load, (1H)
15pF load, (1, 1H)
Measured at V
DD
/2, F
O UT
<66.67MHz 30pF load
Measured at V
DD
/2, F
O UT
<45MHz 15pF load
Measured at V
DD
/2, F
O UT
<100MHz 15pF load
Measured at V
DD
/2V, F
O UT
<45MHz 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Fall Time
(1)
(1H)
t
S K (O )
t
0
t
S K (D)
t
S LEW
t
JIT
t
LO C K
O utput to O utput Skew
(1,1H)
(1)
Delay, C LK IN Rising Edge
to O UT0 Rising Edge
(1)
Device- to- Device Skew
(1)
O utput Slew Rate
(1)
C ycle- to- C ycle Jitter
(1)
(1,1H)
PLL Lock Time
(1)
Measured between 0.8V and 2.0V, 30pF load
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on O UT0 pins of devices
Measured between 0.8V & 2.0V on 1H device
using Test C rt #2
Measured at 66.67 MHz, loaded 30pF load
Measured at 133 MHz, loaded 15pF load
Stable power supply, valid clocks
presented on C LK IN pin
1
200
10 0
1. 0
ms
0
0
40
45
40
45
50
Te s t Conditions
30pF load (1, 1H)
10 . 0
M in.
Typ.
M ax. Units
10 0
13 3
60
55
60
55
2. 2
1. 5 0
1. 5
2. 2
1. 5
1. 5
200
± 300
600
V/ns
ps
ps
ns
%
MHz
Notes:
1.See Switching Waveforms on page 6.
3
PS8592
01/14/02
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2405
Zero Delay Clock Buffer
DC Electrical Characteristics for Commercial Temperature Devices
Parame te r
V
IL
V
IH
I
IL
I
IH
V
O L
V
O H
I
DD
I
DD
De s cription
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
I
O L
= 8mA (1); I
O L
= 12mA (1H)
I
O H
= 8mA (1); I
O H
= 12mA (1H)
Unloaded outputs 100 MHz Select Inputs @ V
DD
or GND
Unloaded outputs, 66.67 MHz, Select inputs at V
DD
or GND
Te s t Conditions
¾
¾
M in.
¾
M ax.
0.8
Units
V
2.0
¾
¾
50
125
0.4
¾
¾
m
A
V
mA
2.4
¾
54
39
¾
¾
AC Electrical Characteristics for Commercial Temperature Device
Parame te rs
F
O
t
DC
t
R
N ame
O utput Frequency
Duty C ycle (1)
Duty C ycle
(1)
(1H)
Rise Time
(1)
@30pF
Rise Time
(1)
@15pF
Rise Time
(1)
@30pF (1H)
t
F
Fall Time
(1)
@30pF
Fall Time
(1)
@15pF
Fall Time
(1)
@30pF (1H)
t
S K (O )
t
0
t
S K (D)
t
S LEW
t
JIT
t
LO C K
O utput to O utput Skew
(1)
(1,1H)
Input to O utput Delay, C LK IN
Rising Edge to O UT0 Rising Edge
(1)
Device to Device Skew
(1)
O utput Slew Rate
(1)
C ycle- to- C ycle Jitter (1,1H)
PLL Lock Time
All outputs equally loaded, V
DD
/2
Measured at V
DD
/2
Measured at V
DD
/2 on O UT0 pins of devices
Measured between 0.8V and 2.0V on 1H
device using Test C ircuit #2
Measured at 66.67 MHz, loaded 30pF outputs
Measured at 133 MHz, loaded 15pF outputs
Stable power supply, valid clocks
presented on C LK IN pins
1
200
10 0
1. 0
0
0
Measured between 0.8V and 2.0V
30pF load
15pF load,
Measured at V
DD
/2, F
O
< 66MHz, 30pF
Measured at V
DD
/2, F
O
< 66MHz, 30pF
40
45
50
50
Te s t Conditions
M in.
10
Typ.
M ax. Units
10 0
13 3
60
55
2. 2
1. 5
1. 5
2. 2
1. 5
1. 5
200
± 300
600
V/ns
ps
ms
ps
ns
MHz
%
Notes:
1. See Switching Waveforms on page 6
4
PS8592
01/14/02
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2405
Zero Delay Clock Buffer
Switching Waveforms
Duty Cycle Timing
VDD/2
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
tR
VDD/2
VDD/2
tSK(O)
2.0V
0.8V
tF
3.3V
0V
thigh
VDD/2
tlow
VDD/2
tDC = thigh
thigh+tlow
Output-Output Skew
OUTPUT
OUTPUT
Device-Device Skew
OUTPUT Device 1
OUTPUT Device 2
VDD/2
VDD/2
tSK(D)
Input-Output Propagation Delay
INPUT
OUTPUT
VDD/2
VDD/2
t0
Test Circuit 1
0.1µF
0.1µF
CLK out
CLOAD
0.1µF
VDD
GND
GND
0.1µF
VDD
GND
Test Circuit 2
1k
9
CLK out
1k
9
GND
10pF
VDD
OUTPUTS
VDD
OUTPUTS
Test Circuit for all parameters except t
SLEW
Test Circuit for t
SLEW
,Output slew rate on –1H device
5
PS8592
01/14/02
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