PI6C185-02BLE datasheet, PDF - EEWORLD Datasheet

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PI6C185-02BLE: DescriptionLow Skew Clock Driver, 6C Series, 7 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16; Categorylogic logic; File Size282KB，6 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/; Environmental Compliance

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PI6C185-02BLE Overview

Low Skew Clock Driver, 6C Series, 7 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16

PI6C185-02BLE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	16
Reach Compliance Code	compliant
ECCN code	EAR99
series	6C
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
length	5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	7
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
minfmax	133 MHz

PI6C185-02BLE Preview

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PI6C185-02B

Precision 1-7 Clock Buffer

Features

High speed: 140 MHz

Low noise non-inverting 1-7 buffer

Supports up to three SDRAM DIMMs

Low skew (<250ps) between any two output clocks

C Serial Configuration interface

Multiple V

, V

pins for noise reduction

3.3V power supply voltage

16-pin TSSOP (L) and QSOP (Q) packages

Description

The PI6C185-02B, a high-speed low-noise 1-7 non-inverting

buffer, is designed for SDRAM clock buffer applications. It is

intended to be used with the PI6C10X clock generator for Intel

Architecture-based Mobile systems.

At power up, all SDRAM outputs are enabled and active. The I2C

Serial control may be used to individually activate/deactivate any

of the seven output drivers.

Note:

Purchase of I2C components from Pericom conveys a license to

use them in an I2C system as defined by Philips.

Block Diagram

SDRAM0

Pin Configuration

SDRAM1

BUF_IN

SDRAM2

SDRAM3

Vdd

SDRAM0

SDRAM1

Vss

BUF_IN

SDRAM2

Vdd

SDATA

16-Pin

L,Q

SDRAM6

SDRAM5

Vss

Vdd

SDRAM4

SDRAM3

Vss

SCLK

SDRAM6

SDATA

SCLOCK

I2C

I/O

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PI6C185-02B

Precision 1-7 Clock Buffer

Pin Description

2,3,6,11,12,15,16

1,7,13

4,10,14

Signal

SDRAM [0...6]

BUF_IN

SDATA

SCLK

Type

I/O

Power

Ground

Qty.

D e s cription

Buffered Clock O utputs

Clock Buffer Input

Serial Data for I

C interface

Serial Clock for I

C interface

3.3V Power Supply

Ground

PI6C185-02B I

C Address Assignment

R/W

PI6C185-02 Serial Configuration Map

Byte0: SDRAM Active/Inactive Register

(1 = enable, 0 = disable)

Byte1: SDRAM Active/Inactive Register

(1 = enable, 0 = disable)

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

SDRAM2

D e s cription

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin#

SDRAM6

SDRAM5

D e s cription

NC (Initialize to 0)

SDRAM1

SDRAM0

NC (Initialize to 0)

SDRAM4

SDRAM3

NC (Initialize to 0)

Note:

Inactive means outputs are held LOWand are disabled

from switching

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PI6C185-02B

Precision 1-7 Clock Buffer

2-Wire I

C Control

The I

C interface permits individual enable/disable of each clock

output and test mode enable.

The PI6C185-02B, a slave receiver device, cannot be read back.

Sub addressing is not supported. To change one of the control

bytes, all preceding bytes must be sent.

Every byte put on the SDATA line must be 8-bits long (MSB first),

followed by an acknowledge bit generated by the receiving

device.

During normal data transfers, SDATA changes only when SCLK is

LOW. Exceptions: A HIGH to LOW transition on SDATA while

SCLK is HIGH indicates a “start” condition; a LOW to HIGH

transition on SDATA while SCLK is HIGH is a “stop” condition

and indicates the end of a data transfer cycle.

Each data transfer is initiated with a start condition and ended with

a stop condition. The first byte after a start condition is always a

7-bit address byte followed by a read/write bit. (HIGH = read from

addressed device, LOW = write to addressed device). If the device’s

own address is detected, PI6C185-02B generates an acknowledge

by pulling SDATA line LOW during ninth clock pulse, then

accepts the following data bytes until another start or stop condition

is detected.

Following acknowledgement of the address byte (0D2H), two more

bytes must be sent:

1. “Command Code” byte &2. “Byte Count” byte.

Although the data bits on these two bytes are “don’t care,” they

must be sent and acknowledged.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Note:

Storage Temperature ..................................... –65°C to +150°C Stresses greater than those listed under MAXIMUM RATINGS

Ambient Temperature with Power Applied ....... –0°C to +70°C may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other

3.3V Supply Voltage to Ground Potential ....... –0.5V to +4.6V

conditions above those indicated in the operational sections of

DC Input Voltage ............................................. –0.5V to +4.6V this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

Supply Current

= +3.465V, Cload = max)

Symbol

Parame te r

Supply Current

Te s t Condition

BUF_IN = 0 MHz

BUF_IN = 66.66 MHz

BUF_IN = 100.0 MHz

M in.

Typ.

M ax.

TBD

Units

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PI6C185-02B

Precision 1-7 Clock Buffer

DC Operating Specifications (V

= +3.3V ±5%, T

= 0°C –70°C)

Symbol

Input Voltage

Input High Voltage

Input Low Voltage

Input Leakage Current

0 < V

< V

2.0

0.3

-5

+0.3

0.8

µA

Parame te r

Condition

M in.

M ax.

Units

= 3.3V ± 5%

Output High Voltage

Output Low Voltage

= 1mA

2.4

0.4

OUT

Input Pin Capacitance

Output pins Capacitance

Pin Inductance

Ambient Temperature

No Airflow

ºC

SDRAM Clock Buffer Operating Specification

Symbol

OHMIN

OHMAX

OLMIN

OLMAX

SDRAM

Parame te r

Pull- up current

Pull- down current

Output rise edge rate

SDRAM only

Output fall edge rate

SDRAM only

Condition

OUT

= 2.0V

OUT

= 3.135V

OUT

= 1.0V

OUT

= 0.4V

3.3V ±5%

@0.4V- 2.4V

3.3V ±5%

@2.4V- 0.4V

1.5

V/ns

M in. Typ. M ax. Units

AC Timing

Symbol

SDKP

SDKH

SDKL

SDRISE

SDFALL

PLH

PHL

PZL

PZH

PLZ

PHZ

Duty Cycle

SDSKW

Parame te r

SDRAM CLK period

SDRAM CLK high time

SDRAM CLK low time

SDRAM CLK rise time

SDRAM CLK fall time

SDRAM Buffer LH prop delay

SDRAM Buffer HL prop delay

SDRAM Buffer Enable delay

SDRAM Buffer Disable delay

Measured at 1.5V

SDRAM Output to Output Skew

66 M Hz

M in.

15.0

5.6

5.3

1.5

1.0

4.0

5.5

8.0

250

M ax.

15.5

100 M Hz

M in.

10.0

3.3

3.1

1.5

1.0

4.0

5.5

8.0

250

M ax.

10.5

133 M Hz

M in.

7.5

1.0

1.5

1.0

4.0

5.5

8.0

250

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M ax.

7.8

Units

V/ns

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Output

Buffer

Test

Point

PI6C185-02B

Precision 1-7 Clock Buffer

Test Load

tSDKP

tSDKH

tSDKL

3.3V

Clocking

Interface

(TTL)

2.4

1.5

0.4

SDRISE

SDFALL

Input

Waveform

plh

Output

Waveform

1.5V

phl

1.5V

Figure 1. Clock Waveforms

Minimum and Maximum Expected Capacitive Loads

Clock

SDRAM

M in Load M ax Load

Units

Note s

SDRAM DIMM Specification

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load.

2. Minimum rise/fall times are guaranteed at minimum specified load.

3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

Design Guidelines to Reduce EMI

1. Place R

series resistors and CI capacitors as close as possible to the respective clock pins. Typical

value for CI is 10pF. R

Series resistor value can be increased to reduce EMI provided that the rise

and fall time are still within the specified values.

2. Minimize the number of “vias” of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

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PI6C185-02BLE Related Products

	PI6C185-02BLE	PI6C185-02BQE
Description	Low Skew Clock Driver, 6C Series, 7 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16	Low Skew Clock Driver, 6C Series, 7 True Output(s), 0 Inverted Output(s), PDSO16, QSOP-16
Is it Rohs certified?	conform to	conform to
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	TSSOP	SOIC
package instruction	TSSOP,	SSOP,
Contacts	16	16
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	6C	6C
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G16	R-PDSO-G16
length	5 mm	4.9 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1
Number of terminals	16	16
Actual output times	7	7
Maximum operating temperature	70 °C	70 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns	0.25 ns
Maximum seat height	1.2 mm	1.75 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.635 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	40
width	4.4 mm	3.9116 mm
minfmax	133 MHz	133 MHz

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