54SHST21CS datasheet, PDF - EEWORLD Datasheet

54SHST21CS: DescriptionAND Gate, HST/T Series, 2-Func, 4-Input, CMOS, CDIP14,; Categorylogic logic; File Size4MB，100 Pages; ManufacturerPlessey Semiconductors Ltd.

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54SHST21CS Overview

AND Gate, HST/T Series, 2-Func, 4-Input, CMOS, CDIP14,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Plessey Semiconductors Ltd.
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	HST/T
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.009 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Prop。Delay @ Nom-Sup	22 ns
propagation delay (tpd)	20 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535V;38534K;883S
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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