U630H04D1K25 datasheet, PDF - EEWORLD Datasheet

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U630H04D1K25: DescriptionNon-Volatile SRAM, 512X8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28; Categorystorage storage; File Size212KB，14 Pages; ManufacturerZentrum Mikroelektronik Dresden AG (IDT)

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U630H04D1K25 Overview

Non-Volatile SRAM, 512X8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28

U630H04D1K25 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Zentrum Mikroelektronik Dresden AG (IDT)
Parts packaging code	DIP
package instruction	DIP, DIP28,.6
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	25 ns
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
length	37.1 mm
memory density	4096 bit
Memory IC Type	NON-VOLATILE SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	28
word count	512 words
character code	512
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512X8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.1 mm
Maximum standby current	0.001 A
Maximum slew rate	0.095 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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U630H04

HardStore

512 x 8 nvSRAM

Features

Packages:

Description

High-performance CMOS nonvo-

latile static RAM 512 x 8 bits

25 ns Access Time

12 ns Output Enable Access Time

Unlimited Read and Write to

SRAM

Hardware STORE Initiation

(STORE Cycle Time < 10 ms)

Automatic STORE Timing

10 STORE cycles to EEPROM

10 years data retention in

EEPROM

Automatic RECALL on Power Up

Hardware RECALL Initiation

(RECALL Cycle Time < 20

µs)

Unlimited RECALL cycles from

EEPROM

Single 5 V

10 % Operation

Operating temperature ranges:

PDIP28 (600 mil)

SOP24 (300 mil)

0 to 70

°C

-40 to 85

°C

CECC 90000 Quality Standard

ESD characterization according

MIL STD 883C M3015.7-HBM

The U630H04 has two separate

modes of operation: SRAM mode

and nonvolatile mode, determined

by the state of the NE pin.

In SRAM mode, the memory ope-

rates as an ordinary static RAM. In

nonvolatile operation, data is trans-

ferred in parallel from SRAM to

EEPROM or from EEPROM to

SRAM. In this mode SRAM

functions are disabled.

The U630H04 is a fast static RAM

(25 ns), with a nonvolatile electri-

cally erasable PROM (EEPROM)

element incorporated in each static

memory cell. The SRAM can be

read and written an unlimited num-

ber of times, while independent

nonvolatile

data

resides

EEPROM.

Data transfers from the SRAM to

the EEPROM (the STORE opera-

tion), or from the EEPROM to the

SRAM (the RECALL operation) are

initiated through the state of the NE

pin.

The U630H04 combines the high

performance and ease of use of a

fast SRAM with nonvolatile data

integrity.

Once a STORE cycle is initiated,

further input or output are disabled

until the cycle is completed.

Internally, RECALL is a two step

procedure. First, the SRAM data is

cleared and second, the nonvola-

tile information is transferred into

the SRAM cells.

The RECALL operation in no way

alters the data in the EEPROM

cells. The nonvolatile data can be

recalled an unlimited number of

times.

Pin Configuration

Pin Description

n.c.

DQ0

DQ1

DQ2

VSS

PDIP

VCC

n.c.

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

VSS

VCC

n.c.

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A8

DQ0 - DQ7

VCC

VSS

n.c.

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Nonvolatile Enable

Power Supply Voltage

Ground

not connected

SOP

Top View

August 07, 1998

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