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UPD4516421AG5-A10L-9NF

Description
Synchronous DRAM, 4MX4, 6ns, MOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
Categorystorage    storage   
File Size1MB,88 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Download Datasheet Parametric View All

UPD4516421AG5-A10L-9NF Overview

Synchronous DRAM, 4MX4, 6ns, MOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44

UPD4516421AG5-A10L-9NF Parametric

Parameter NameAttribute value
MakerELPIDA
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts44
Reach Compliance Codeunknown
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G44
length18.32 mm
memory density16777216 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals44
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX4
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.16 mm
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4516421A, 4516821A, 4516161A for Rev.P
16M-bit Synchronous DRAM
2-banks, LVTTL
(2
Description
Features
Pulsed interface
• ×4, ×8, ×16
organization
Document No. E0122N10 (Ver.1.0)
(Previous No. M12939EJ3V0DS00)
Date Published May 2001 CP (K)
Printed in Japan
The
µ
PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 44-pin TSOP (II) (× 4,
×
8) and 50-pin TSOP (II) (× 16).
memories, organized as 2,097,152
×
4
×
2, 1,048,576
×
8
×
2, 524,288
×
16
×
2 (word
×
bit
×
bank), respectively.
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Possible to assert random column address in every cycle
Dual internal banks controlled by A11(Bank Select)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
CBR (Auto) refresh and self refresh
Single 3.3 V
±
0.3 V power supply
2,048 refresh cycles / 32 ms
Automatic precharge and controlled precharge
LVTTL compatible inputs and outputs
Burst termination by Burst stop command and Precharge command
/
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
R
3U
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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