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IDT70T631S15DDG

Description
Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
Categorystorage    storage   
File Size227KB,27 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT70T631S15DDG Overview

Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144

IDT70T631S15DDG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
Contacts144
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time15 ns
I/O typeCOMMON
JESD-30 codeS-PQFP-G144
JESD-609 codee3
length20 mm
memory density4718592 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Number of functions1
Number of ports2
Number of terminals144
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP144,.87SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5,2.5/3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.01 A
Minimum standby current2.4 V
Maximum slew rate0.305 mA
Maximum supply voltage (Vsup)2.6 V
Minimum supply voltage (Vsup)2.4 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width20 mm
Features
HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
IDT70T633/1S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
Functional Block Diagram
UB
L
LB
L
Full hardware support of semaphore signaling between
ports on-chip
On-chip port arbitration logic
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
UB
R
LB
R
R/
W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/
W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
512/256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
18L
(1)
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
18R
(1)
A
0R
TDI
OE
L
CE
0L
CE
1L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0R
CE
1R
TDO
JTAG
TCK
TMS
TRST
R/W
L
R/W
R
BUSY
L(2,3)
SEM
L
INT
L(3)
ZZ
(4)
(4)
ZZ
L
ZZ
R
NOTES:
CONTROL
LOGIC
1. Address A
18
x is a NC for IDT70T631.
2.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
3
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx,
M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
BUSY
R(2,3)
M/S
SEM
R
INT
R(3)
5670 drw 01
JANUARY 2006
DSC-5670/5
1
©2006 Integrated Device Technology, Inc.
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