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U62H256S1A55G1

Description
Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP-28
Categorystorage    storage   
File Size85KB,9 Pages
ManufacturerAlliance Memory
Environmental Compliance  
Download Datasheet Parametric View All

U62H256S1A55G1 Overview

Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP-28

U62H256S1A55G1 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAlliance Memory
Parts packaging codeSOIC
package instructionSOP,
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time55 ns
JESD-30 codeR-PDSO-G28
length18.1 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height2.54 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width8.75 mm
U62H256
Automotive Fast 32K x 8 SRAM
Features
F
32768 x 8 bit static CMOS RAM
F
35 and 55 ns Access Time
F
Common data inputs and
F
F
Description
The U62H256 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
is available. The data outputs have
no preferred state. The Read cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
F
F
F
F
F
F
F
F
data outputs
Three-state outputs
Typ. operating supply current
35 ns: 45mA
55 ns: 30mA
Standby current < 50 µA at 125°C
TTL/CMOS-compatible
Power supply voltage 5 V
Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: SOP28 (300/330 mil)
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
SOP
22
21
20
19
18
17
16
15
Top View
November 01, 2001
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