K4S510632B-TL75 datasheet, PDF

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K4S510632B-TL75: DescriptionSynchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size119KB，11 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4S510632B-TL75 Overview

Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

K4S510632B-TL75 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.004 A
Maximum slew rate	0.235 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

K4S510632B-TL75 Preview

K4S510632B

Preliminary

CMOS SDRAM

Stacked 512Mbit SDRAM

32M x 4bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.1

March 2001

* Samsung Electronics reserves the right to change products or specification without

Rev. 0.1 Mar.2001

K4S510632B

Preliminary

CMOS SDRAM

Revision History

Revision 0.0 (Feb., 2001)

Revision 0.1 (Mar,, 2001)

• Changed the input capacitance of CS0~1

Rev. 0.1 Mar.2001

K4S510632B

32M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

Preliminary

CMOS SDRAM

GENERAL DESCRIPTION

The K4S510632B is 536,870,912 bits synchronous high data rate

Dynamic RAM organized as 4 x 33,554,432 words by 4 bits, fabri-

cated with SAMSUNG's high performance CMOS technology. Syn-

chronous design allows precise cycle control with the use of

system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system appli-

cations.

ORDERING INFORMATION

Part No.

K4S510632B-TC/L75

K4S510632B-TC/L1H

K4S510632B-TC/L1L

Max Freq.

133MHz(CL=3)

100MHz(CL=2)

100MHz(CL=3)

LVTTL

Interface

Package

54pin

TSOP(II)

FUNCTIONAL BLOCK DIAGRAM

CLK,CAS,RAS

/WE,CKE,DQM

/CS1

64Mx4

/CS0

DQ0 ~ DQ3

A0~A12,BA0,BA1

* Samsung Electronics reserves the right to change products or specification without notice.

Staktek’ stacking technology is Samsung’ stacking technology of choice.

Rev. 0.1 Mar.2001

K4S510632B

PIN CONFIGURATION (Top view)

N.C

DDQ

N.C

DQ0

SSQ

N.C

DDQ

N.C

DQ1

SSQ

N.C

CS1

CAS

RAS

CS0

BA0

BA1

A10/AP

N.C

SSQ

N.C

DQ3

DDQ

N.C

SSQ

N.C

DQ2

DDQ

N.C

N.C/RFU

DQM

CLK

CKE

A12

A11

Preliminary

CMOS SDRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

CS0~1

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

CKE

Clock enable

~ A

~ BA

RAS

CAS

DQM

DDQ

SSQ

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

Rev. 0.1 Mar.2001

K4S510632B

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

Preliminary

CMOS SDRAM

Unit

°C

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes : 1. V

(max) = 5.6V AC. The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

RAS, CAS, WE, DQM

Address,CKE

CS0~1

~ DQ

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

5.0

2.5

8.0

Max

9.0

10.0

6.5

14.0

Unit

Note

Rev. 0.1 Mar.2001

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Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
Contacts	54	54	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	6 ns	6 ns	5.4 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	100 MHz	100 MHz	133 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	e0	e0	e0	e0	e0
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	4	4	4	4	4	4
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	54	54	54	54	54	54
word count	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words
character code	128000000	128000000	128000000	128000000	128000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128MX4	128MX4	128MX4	128MX4	128MX4	128MX4
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
Maximum slew rate	0.235 mA	0.225 mA	0.225 mA	0.235 mA	0.225 mA	0.225 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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