PF495-07
SLA100X Series
Low Voltage Gate Array
ge
lta
Vo n
w ratio s
Lo pe ct
O rodu
P
qLow
Power Silicon Gate CMOS
qLow
Operating Voltages
qCMOS-Compatible
I/O
qLow
Voltage Operational Oscillator on Chip
s
DESCRIPTION
The SLA100X series gate arrays are fabricated utilizing our low threshold CMOS technology. Six devices, with
raw gates ranging from 1,530 gates up to 7,750 gates, are available in a range of packages. All devices have
level-shifter and low-power oscillator on chip.
Designers can select 3.0V or 1.5V operation, making the devices in this series ideal for portable equipment and
other low and very-low power applications. Eight power / ground pins are dedicated.
SLA100X series LSls can be designed with the same schematic capture and simulation tools as the SEIKO
EPSON SLA9000F series gate arrays.
s
FEATURES
q
Channeled Array
q
Adopting 2.0µm silicon gate CMOS with 2-metal layers
q
Low power consumption (V
DD
= 0.9V to 6.0V)
q
Available dual-power supplies (built-in level shift circuit)
q
Available built-in oscillator circuit
s
PRODUCT LINEUP
Master
Features
Total BCs (Raw Gates)
Usable BCs
Number of PADs
Number of I/O PADs
Number of Power Supply Pins
Propagation Delay Coefficient
Internal Gates
Input Buffers
Output Buffers
SLA115X
1,530
1,300
78
70
SLA121X
2,108
1,786
90
82
SLA132X
3,276
2,784
112
104
SLA147X
4,704
3,998
136
128
SLA159X
5,980
5,083
158
150
SLA177X
7,750
6,587
178
170
Propagation
Delay
I/O Level
Input Mode
Output Mode
8
8
8
8
8
8
The coefficient value is calculated by multiplying the coefficient value of Max. or Min. for Typ.
value for VDD = 1.5V described in the SLA100X series MSI CELL Library by lowest value or
highest value of using voltage. For more information about the coefficient value, contact our
sales office for technical support.
tpd = 8.5ns (standard at 1.5V), tpd = 3.0ns (standard at 3.0V)
tpd = 12.0ns (standard at 1.5V), tpd = 4.0ns (standard at 3.0V)
tpd = 40.0ns (standard at 1.5V), tpd = 14.0ns (standard at 3.0V) CL = 50pF
CMOS
CMOS, Pull-up/Pull-down, Schmitt, Dual power level interface (Level shifter)
Normal, Open drain, 3-state, Bi-directional, Dual power level interface (Level shifter)
1
SLA100X
Series
s
ABSOLUTE MAXIMUM RATINGS
Rating
Supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
V
DD1,2
V
I
V
O
T
stg
Value
– 0.5 to 7.0
– 0.5 to V
DD1,2
+0.5
– 0.5 to V
DD1,2
+0.5
– 65 to 150
(V
SS=
0V)
Unit
V
V
V
°C
s
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
V
DD1
Supply voltage
V
DD2
V
DD1
V
DD2
Operating voltage
Operating temperature
V
DD1,2
Topr
Remark
1.5V
3V (V
DD1
=1.5V)
3V
5V (V
DD1
=3.0V)
Min.
1.35
2.70
2.70
4.50
0.90
0
Typ.
1.50
3.00
3.00
5.00
–
–
Max.
1.65
3.30
3.30
5.50
6.00
70
Unit
V
V
V
V
V
°C
Note: Please contact your local SEIKO EPSON sales representative to operate at V
DD1
=1.5V and/or V
DD2
=5.0V.
s
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
I
DDS1
I
DDS1
Standby supply current
I
DDS2
I
DDS2
V
OH
High level output volrage
V
OH
V
OH
V
OL
Low level output voltage
V
OL
V
OL
V
IH
High level input voltage
V
IH
V
IH
V
IL
Low level input voltage
V
IL
V
IL
Input leakage current
I
LI
Condition
Static state, V
DD1
=1.5V
Static state, V
DD1
=3.0V
Static state, V
DD2
=3.0V
Per one level shifter
Static state, V
DD2
=5.0V
Per one level shifter
V
DD1
=1.5V, I
OH
= – 0.23mA
V
DD1,2
=3.0V, I
OH
= – 0.6mA
V
DD2
=4.5V, I
OH
= – 1.2mA
V
DD1
=1.5V, I
OL
=0.7mA
V
DD1
,
2
=3.0V, I
OL
=1.9mA
V
DD2
=4.5V, I
OL
=4.0mA
V
DD1
=1.5V
V
DD1
,
2
=3.0V
V
DD2
=5.0V
V
DD1
=1.5V
V
DD1
,
2
=3.0V
V
DD2
=5.0V
Min.
–
–
–
–
1.3
2.7
4.1
–
–
–
1.25
2.40
3.5
–
–
–
–1
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Ta=0 to 70°C)
Max.
200
1.0
90
100
–
–
–
0.2
0.3
0.4
–
–
–
0.25
0.60
1.5
1
Unit
nA
µA
nA
nA
V
V
V
V
V
V
V
V
V
V
V
V
µA
NOTE: I
DD2
is voltage supplied from V
DD2
for I/O cell using level shifter.
V
DD1
: Supply voltage for MSI on chip.
V
DD2
: External voltage.
V
DD2
≥V
DD1
2
SLA100X
Series
s
CHARACTERISTICS CURVES
q
Output Current
I
OL
vs. V
OL
(mA)
12
10
I
OL
8
6
4
2
0
0
1.0
0.2 0.4 0.6 0.8 1.0 1.2
(V)
V
OL
2.0
1.5
3.0
Ta=25
V
DD
=5.0V
V
DD
=5.0V
Ta=25
3.0
(V
DD
–V
OH)
vs. I
OH
V
DD
–V
OH
(V)
1.2 1.0 0.8 0.6 0.4 0.2 0
0
1.0
1.5
1
2.0
2
3
4
5
6
(mA)
TYPE1
TYPE2
TYPE3
I
OH
+ V
DD
IBC
V
I
V
I
=V
DD
I
OH
V
I
=V
SS
I
OL
OB2
I
OH
I
OL
A
V
OH
, V
OL
– V
SS
I
OH
(mA)
–0.2
–0.6
–1.2
I
OL
(mA)
0.6
1.9
1.9
V
DD
=V
DD1
, V
DD2
q
t
pd
, t
r
, t
f –
C
L
t
pd
vs. C
L
(ns)
120
100
t
pd
80
60
40
20
0
0
t
PHL
1.5V
t
PLH
3.0V
t
PHL
3.0V
t
PLH
5.0V
t
PHL
5.0V
20 40 60 80 100 120
(pF)
C
L
t
PLH
1.5V
(ns)
200
180
160
140
120
100
80
60
40
20
t
r,
t
f
vs. C
L
t
r
1.5V
IN
IBC
+ V
DD
O2B
OUT
C
L
– V
SS
t
r
, t
f
t
r
3.0V
t
f
1.5V
t
r
5.0V
t
f
3.0V
t
f
5.0V
0 20 40 60 80 100 120
(pF)
C
L
Measuring circuit
IN
V
DD
2
90
V
DD
V
DD
10
V
pp
=V
DD
Ta=25[°C]
2
t
PHL
V
DD
=V
DD1,
V
DD2
OUT
t
PLH
q
Propagation delay, Power consumption
t
pd
vs. V
DD1
(%)
200
180
160
140
120
100
80
60
40
20
0
(%)
120
t
pd
Ta=25
V
DD
=1.5V, t
pd
=100
110
100
90
80
0
1
2
3 4
V
DD1
5
6
(V)
–20 0 20 40 60 80
(°C)
Ta
10
–7
10
–8
10
3
t
pd
vs. Ta
V
DD1
=1.5V–3.0V
Ta=25 , t
pd
=100
P
(W)
10
–4
10
–5
10
–6
p vs. f
(p: power consumption)
V
DD1
=5.0V
2 input NAND
gate/piece
3.0
1.5
Ta=25
1.0
t
pd
10
4
10
5
f
10
6
10
7
(Hz)
3
SLA100X
Series
q
Propagation delay Characteristics for Level Shift Circuit
t
pd
vs. V
DD2
Level shift circuit
(ns)
120
100
t
pd
t
PLH
V
DD1
=1.5V
Ta=25°C
t
pd vs.
Ta
Level shift circuit
(%)
130
120
t
pd
V
DD1
=
1.5V, V
DD2
=
3.0V
Ta
=
25 , t
pd
=
100
t
PLH
t
PHL
80
60
t
PHL
V
DD1
=1.5V
40
t
PLH
V
DD1
=3.0V
110
100
90
20
0
0
t
PHL
V
DD1
=3.0V
1
2
3
V
DD2
4
5
6
(V)
80
–20 0
20 40 60 80
Ta
(°C)
s
INTERFACE EXAMPLE FOR LEVEL SHIFT CIRCUIT
V
DD2
V
DD1
OB2
IVC
LSI (A)
BC2
IVC
OB2
SLA100X
OB21
IVC1
IVC
OB2
LSII (B)
BC2
BC2
V
DD1
signal of V
DD
Line
BC21
V
DD2
signal of V
DD
Line
V
SS
,,
,,
V
DD2
≥V
DD1
4
SLA100X
Series
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical
products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no
representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the
Ministry of International Trade and Industry or other approval from another government agency.
All product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©Seiko Epson Corporation 1998 All rights reserved.
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Phone: +81-(0)42-587-5816
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I
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II
(Asia)
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