IBM11M4730C4M x 72 E12/10, 5.0V, Au.
IBM11M1645B
1M x 64 DRAM MODULE
Features
• 168 Pin JEDEC Standard, 8 Byte Dual In-line
Memory Module
• 1Mx64 Extended Data Out Page Mode DIMM
• Performance:
-60
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
EDO Mode Cycle Time
60ns
20ns
35ns
104ns
25ns
-70
70ns
25ns
40ns
124ns
30ns
• Optimized for byte-write non-parity applications
• System Performance Benefits:
-
-
-
-
-
Buffered inputs (except RAS, Data)
Reduced noise (32 V
SS
/V
CC
pins)
4 Byte Interleave enabled
Byte write, byte read accesses
Buffered PDs
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
• 1024 refresh cycles distributed across 64ms
• 10/10 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.354"
• DRAMS in SOJ Package
• All inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
• Single 3.3V
±
0.3V or 5V
±
0.5V Power Supply
• Au contacts
Description
IBM11M1645B is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) which is
organized as a 1Mx64 high speed memory array
designed with EDO DRAMs for non-parity applica-
tions. The DIMM uses 16 1Mx4 EDO DRAMs in
SOJ packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 25ns for 60ns DRAM modules.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and
RAS
signals are not
buffered, which preserves the DRAM access speci-
fications of 60ns and 70ns.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide informa-
tion for the entire DIMM bank. For example, if a x64
parity DIMM were inserted into a bank of x72 parity
DIMMs, ID0 (grounded) would indicate that at least
one DIMM in that memory bank is x64, and if the
memory controller is designed to do so, all DIMMs
in that memory bank will function as x64s.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x72 parity (5V)
and ECC DIMMs (5V and 3.3V).
Card Outline (3.3V)
(Front)
(Back)
1
85
10 11
94 95
40 41
124 125
See Detail A
for 5.0V Version
84
168
Detail A
75H3412
SA14-4619-00
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 28
IBM11M1645B
1M x 64 DRAM MODULE
Pin Description
RAS0, RAS2
CAS0 - CAS7
WE0, WE2
OE0, OE2
A0, B0, A1 - A9
DQx
V
CC
V
SS
NC
PD1 - PD8
PDE
ID0 - ID1
Row Address Strobe
Column Address Strobe (Buffered)
Read/write Input (Buffered)
Output Enable (Buffered)
Address Inputs (Buffered)
Data Input/Output
Power (3.3V or 5.0V)
Ground
No Connect
Presence Detects (Buffered)
Presence Detect Enable
ID Bits
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Front
Side
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
NC
NC
V
CC
WE0
CAS0
CAS2
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
NC
NC
V
CC
NC
NC
Pin#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Back
Side
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
NC
NC
V
CC
NC
CAS1
CAS3
NC
NC
V
SS
A1
A3
A5
A7
A9
NC
NC
V
CC
NC
B0
Pin#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
Side
V
SS
OE2
RAS2
CAS4
CAS6
WE2
V
CC
NC
NC
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
DQ24
NC
NC
NC
NC
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
Pin#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
Side
V
SS
NC
NC
CAS5
CAS7
PDE
V
CC
NC
NC
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
NC
NC
NC
NC
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
Note:
All pin assignments are consistent for all 8 Byte versions.
Ordering Information
Part Number
IBM11M1645B-60J
1Mx64
IBM11M1645B-70J
Organization
Speed
60ns
70ns
Addr.
10/10
Leads
Au
Dimension
5.25”x1.0”x 0.354”
Power
5.0V
Notes
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H3412
SA14-4619-00
Revised 6/96
Page 2 of 28
IBM11M1645B
1M x 64 DRAM MODULE
Block Diagram
OE0
WE0
CAS0
DQ0
DQ1
DQ2
DQ3
RAS0
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
OE2
WE2
CAS4
DQ36
DQ37
DQ38
DQ39
WE
OE
DQ40
DQ41
DQ42
DQ43
RAS2
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
D0
D8
RAS
RAS
WE
OE
DQ4
DQ5
DQ6
DQ7
D1
D9
CAS1
DQ9
DQ10
DQ11
DQ12
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
CAS5
DQ45
DQ46
DQ47
DQ48
WE
OE
DQ49
DQ50
DQ51
DQ52
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
D2
D10
RAS
RAS
WE
OE
DQ13
DQ14
DQ15
DQ16
D3
D11
CAS2
DQ18
DQ19
DQ20
DQ21
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
CAS6
D4
DQ54
DQ55
DQ56
DQ57
WE
OE
DQ58
DQ59
DQ60
DQ61
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
D12
RAS
RAS
WE
OE
DQ22
DQ23
DQ24
DQ25
D5
D13
CAS3
DQ27
DQ28
DQ29
DQ30
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
CAS7
D6
DQ63
DQ64
DQ65
DQ66
WE
OE
DQ67
DQ68
DQ69
DQ70
CAS
I/O 0
I/O 1
I/O 2
I/O 3
CAS
I/O 0
I/O 1
I/O 2
I/O 3
RAS
WE
OE
VSS
PDE
A1 - AN
A0
B0
RAS
WE
OE
PD 1-8 (when = 0, 1=NC)
A1-AN: DRAMS D0 - D15
A0: DRAMS D0-D7
A0: DRAMS D8-D15
D14
RAS
DQ31
DQ32
DQ33
DQ34
D7
D15
VCC
VSS
D0 - D15, Buffers
D0 - D15, Buffers
75H3412
SA14-4619-00
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 28
IBM11M1645B
1M x 64 DRAM MODULE
Truth Table
Function
Standby
Read
Early-Write
Late-Write
RMW
EDO Page Mode - Read
1st Cycle
Subsequent Cycles
EDO Page Mode - Write
1st Cycle
Subsequent Cycles
EDO Page Mode - RMW
1st Cycle
Subsequent Cycles
RAS-Only Refresh
CAS-Before-RAS Refresh
Hidden Refresh
Read
Write
Read Presence Detects
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H→L
L→H→L
L→H→L
X
CAS
H→X
L
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
L
X
WE
X
H
L
H→L
H→L
H
H
L
L
H→L
H→L
X
H
H
H
X
OE
X
L
X
H
L→H
L
L
X
X
L→H
L→H
X
X
L
X
X
Row
Address
X
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Row
Row
X
Column
Address
X
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
N/A
X
Col
Col
X
PDE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DQx
High Impedance
Valid Data Out
Valid Data In
Valid Data In
Valid Data Out,
Valid Data In
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Valid Data Out,
Valid Data In
Valid Data Out,
Valid Data In
High Impedance
High Impedance
Data Out
Data In
Not Affected
(PD Bits Valid)
Presence Detect
Pin
PD1 (PD1 - PD4: Addressing/Density)
PD2
PD3
PD4
PD5 (EDO Detection)
PD6 (PD6 - PD7: Speed)
PD7
PD8 (Parity/ECC Designator)
ID0 (DIMM Type/Width)
ID1 (Refresh Mode)
1. PD1-8 are buffered outputs (0 = driven to V
OL
, 1 = open)
2. ID0-1 are unbuffered outputs (0 = V
SS
, 1 = open)
3. PDE should be tied high or low at system level if not used
-60
0
0
1
0
1
1
1
1
0
0
-70
0
0
1
0
1
0
1
1
0
0
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H3412
SA14-4619-00
Revised 6/96
Page 4 of 28
IBM11M1645B
1M x 64 DRAM MODULE
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
OPR
T
STG
P
D
I
OUT
I
OUTPD
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Short Circuit Output Current (PD)
Rating (3.3V)
-0.5 to +4.1
-0.5 to min (V
CC
+ 0.5, 4.1)
-0.5 to min (V
CC
+ 0.5, 4.1)
0 to +70
-55 to +125
5.5
50
60
Rating (5.0V)
-1.0 to +6.0
-0.5 to min (V
CC
+ 0.5, 6.0)
-0.5 to min (V
CC
+ 0.5, 6.0)
0 to +70
-55 to +125
7.5
50
60
Units
V
V
V
Notes
1
1
1
1
1
1
1
1
°
C
°
C
W
mA
mA
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating con-
dition for extended periods may affect reliability.
Recommended DC Operating Conditions
(T
A
= 0 to 70
°
C)
3.3V
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
3.0
2.0
-0.3
Typ
3.3
—
—
Max
3.6
V
CC
+ 0.3
0.8
Min
4.5
2.4
-0.5
5.0V
Typ
5.0
—
—
Max
5.5
V
CC
+ 0.5
0.8
Units
V
V
V
Notes
1
1, 2
1, 2
1. All voltages referenced to V
SS.
2. V
IH
may overshoot to V
CC
+ 1.2V for pulse widths of
≤
4.0ns with 3.3 Volt, or V
CC
+ 2.0V for pulse widths of
≤
4.0ns (or V
CC
+ 1.0V
for
≤
8.0ns) with 5.0 Volt. Additionally, V
IL
may undershoot to -1.2V for pulse widths
≤
4.0ns with 3.3 Volt, or to -2.0V for pulse
widths
≤
4.0ns (or -1.0V for
≤
8.0ns) with 5.0 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC ref-
erence.
Capacitance
(T
A
= 0 to +70
°
C, V
CC
= 3.3V
±
0.3V or 5.0V
±
0.5V)
Symbol
C
I1
C
I2
C
I3
C
I4
C
IO1
C
O1
C
O2
Parameter
Input Capacitance (A0, B0, A1-A9)
Input Capacitance (RAS)
Input Capacitance (CAS, WE, OE)
Input Capacitance (PDE)
Input/Output Capacitance (DQ
X
)
Output Capacitance (PD)
Output Capacitance (ID)
Max
13
60
13
18
15
15
5
Units
pF
pF
pF
pF
pF
pF
pF
75H3412
SA14-4619-00
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 28
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