IS61LPD25632D-150TQ datasheet, PDF

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IS61LPD25632D-150TQ: DescriptionCache SRAM, 256KX32, 3.8ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size151KB，22 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LPD25632D-150TQ Overview

Cache SRAM, 256KX32, 3.8ns, CMOS, PQFP100, TQFP-100

IS61LPD25632D-150TQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Maximum clock frequency (fCLK)	150 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	8388608 bit
Memory IC Type	CACHE SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.105 A
Minimum standby current	3.14 V
Maximum slew rate	0.37 mA
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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IS61SPD25632T/D IS61LPD25632T/D

IS61SPD25636T/D IS61LPD25636T/D

IS61SPD51218T/D IS61LPD51218T/D

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS PIPELINE,

DOUBLE-CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control using

MODE input

• Three chip enable option for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

• 3.3V I/O For SPD

• 2.5V I/O For LPD

• Double cycle deselect

• Snooze MODE for reduced-power standby

• T version (three chip selects)

• D version (two chip selects)

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2000

DESCRIPTION

The

ISSI

IS61SPD25632, IS61SPD25636, S61SPD51218,

IS61LPD25632, IS61LPD25636, and IS61LPD51218 are

high-speed, low-power synchronous static RAMs designed

to provide a burstable, high-performance, secondary cache for

the Pentium™, 680X0™, and PowerPC™ microprocessors.

The IS61SPD25632 and IS61LPD25632 are organized as

262,144 words by 32 bits and the IS61SPD25636 and

IS61LPD25636 are organized as 262,144 words by 36 bits.

The IS61SPD51218 and IS61LPS51218 are organized as

524,288 words by 18 bits. Fabricated with

ISSI

's advanced

CMOS technology, the device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous inputs

pass through registers controlled by a positive-edge-triggered

single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE).input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-166*

3.5

166

-150

3.8

6.7

150

-133

7.5

133

-5

100

Units

MHz

*This speed available only in SPD version

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION

04/17/01

Rev. 00A

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