TSPC106AVGB/Q83CG datasheet, PDF

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TSPC106AVGB/Q83CG: DescriptionPCI Bus Controller, CMOS, CBGA303, 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-303; CategoryThe embedded processor and controller Microcontrollers and processors; File Size505KB，39 Pages; ManufacturerAtmel (Microchip)

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TSPC106AVGB/Q83CG Overview

PCI Bus Controller, CMOS, CBGA303, 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-303

TSPC106AVGB/Q83CG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	BGA, BGA303,19X16,50
Contacts	303
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	32
Bus compatibility	60X; POWERPC 601; POWERPC 603; POWERPC 604
maximum clock frequency	83.3 MHz
External data bus width	64
JESD-30 code	R-CBGA-B303
JESD-609 code	e0
length	25 mm
Number of terminals	303
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Encapsulate equivalent code	BGA303,19X16,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
power supply	3.3 V
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	3.16 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn10Pb90)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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Features

•

Processor Bus Frequency Up to 66 MHz and 83.3 MHz

64-bit Data Bus and 32-bit Address Bus

L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes

Provides Support for Either Asynchronous SRAM, Burst SRAM

or Pipelined Burst SRAM

Compliant with PCI Specification, Revision 2.1

PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible

IEEE 1149.1-compliant, JTAG Boundary-scan Interface

Max = 1.7 Watts (66 MHz), Full Operating Conditions

Nap, Doze and Sleep Modes Reduce Power Consumption

Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards

Upscreenings Based on Atmel Standards

Full Military Temperature Range (-55°C

≤

+125°C)

Industrial Temperature Range (-40°C

≤

+110°C)

= 3.3V ± 5%

Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI)

(CI-CGA) Package

PCI Bridge/

Memory

Controller

TSPC106

Description

The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-com-

patible interface between a 60x processor, a secondary (L2) cache or up to a total of

four additional 60x processors, the PCI bus and main memory.

PCI support allows system designers to rapidly design systems using peripherals

already designed for PCI.

The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full

interface compatibility with TTL devices.

The TSPC106 integrates system testability and debugging features via JTAG bound-

ary-scan capability.

Note:

In this document, the term “60x” is used to denote a 32-bit microprocessor from the

PowerPC family that conforms to the bus interface of the PowerPC 601

, PowerPC

603

™

or PowerPC 604

™

microprocessors. This does not include the PowerPC 602

™

microprocessor that has a multiplexed address/data bus. 60x processors implement

the PowerPC architecture as it is specified for 32-bit addressing, providing 32-bit effec-

tive (logical) addresses, integer data types of 8, 16 and 32 bits, and floating-point data

types of 32 and 64 bits (single-precision and double-precision).

Rev. 2102A–06/01

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