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Datasheet> All Categories > Analog mixed-signal IC> converter> AD9433BSQ-125
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AD9433BSQ-125

Description
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52
CategoryAnalog mixed-signal IC    converter   
File Size2MB，25 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric Compare View All

AD9433BSQ-125 Overview

1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52

AD9433BSQ-125 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerRochester Electronics
Parts packaging codeQFP
package instructionHLQFP,
Contacts52
Reach Compliance Codeunknown
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQFP-G52
JESD-609 codee0
length10 mm
Maximum linear error (EL)0.0317%
Humidity sensitivity level3
Number of analog input channels1
Number of digits12
Number of functions1
Number of terminals52
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHLQFP
Package shapeSQUARE
Package formFLATPACK, HEAT SINK/SLUG, LOW PROFILE
Peak Reflow Temperature (Celsius)240
Sampling rate125 MHz
Sample and hold/Track and holdTRACK
Maximum seat height1.6 mm
Nominal supply voltage5 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm

AD9433BSQ-125 Preview

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FEATURES
IF Sampling up to 350 MHz
SNR = 67.5 dB, f
IN
up to Nyquist @ 105 MSPS
SFDR = 83 dBc, f
IN
70 MHz @ 105 MSPS
SFDR = 72 dBc, f
IN
150 MHz @ 105 MSPS
2 V p-p Analog Input Range Option
On-Chip Clock Duty Cycle Stabilization
On-Chip Reference and Track/Hold
SFDR Optimization Circuit
Excellent Linearity:
DNL = 0.25 LSB (Typ)
INL = 0.5 LSB (Typ)
750 MHz Full Power Analog Bandwidth
Power Dissipation = 1.35 W Typical @ 125 MSPS
Two’s Complement or Offset Binary Data Format
5.0 V Analog Supply Operation
2.5 V to 3.3 V TTL/CMOS Outputs
APPLICATIONS
Cellular Infrastructure Communication Systems
3G Single and Multicarrier Receivers
IF Sampling Schemes
Wideband Carrier Frequency Systems
Point to Point Radios
LMDS, Wireless Broadband
MMDS Base Station Units
Cable Reverse Path
Communications Test Equipment
Radar and Satellite Ground Systems
GENERAL INTRODUCTION
12-Bit, 105 MSPS/125 MSPS
IF Sampling A/D Converter
AD9433
FUNCTIONAL BLOCK DIAGRAM
V
CC
AD9433
PIPELINE
ADC
12
V
DD
AIN
AIN
T/H
OUTPUT
STAGING
D11–D0
12
ENCODE
ENCODE
DFS
ENCODE
TIMING
REF
SFDR
GND
REF REF
OUT IN
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user-
selectable for binary or two’s complement and provides an
overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a thermally enhanced 52-lead plastic quad flatpack
specified over the industrial temperature range (–40°C to
+85°C) and is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
The AD9433 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is designed
for ease of use. The product operates up to 125 MSPS conver-
sion rate and is optimized for outstanding dynamic performance
in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
A user-selectable, on-chip proprietary circuit optimizes spurious-
free dynamic range (SFDR) versus signal-to-noise-and-distortion
(SINAD) ratio performance for different input signal frequencies,
providing as much as 83 dBc SFDR performance over the dc
to 70 MHz band.
1.
IF Sampling
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G Wideband
Cellular IF sampling receivers.
2. Pin-Compatibility
This ADC has the same footprint and pin layout as the
AD9432, 12-Bit 80/105 MSPS ADC.
3. SFDR Performance
A user-selectable on-chip circuit optimizes SFDR performance
as much at 85 dBc from dc to 70 MHz.
4. Sampling Rate
At 125 MSPS, this ADC is ideally suited for current wireless
and wired broadband applications such as LMDS/MMDS
and cable reverse path.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9433–SPECIFICATIONS
DC SPECIFICATIONS
(V
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
THERMAL DRIFT
Offset Error
Gain Error
1
Reference
REFERENCE
Internal Reference Volatge (VREFOUT)
Output Current (VREFOUT)
Input Current (VREFIN)
ANALOG INPUTS
Differential Input Voltage Range
(AIN, AIN)
Common-Mode Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
V
CC
V
DD
Power Dissipation
3
Power Supply Rejection Ratio (PSRR)
IV
CC2
IV
DD2
ENCODE INPUTS
Internal Common-Mode Bias
Differential Input (ENC –
ENC)
Input Voltage Range
Input Common-Mode Range
Input Resistance
Input Capacitance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input High Current (VIN = 5 V)
Input Low Current (VIN = 0 V)
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
Full
Full
25 C
25 C
Full
25 C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25 C
Full
Full
Full
Full
Full
Full
Full
25 C
Full
Full
Full
Full
Full
Full
VI
VI
I
I
VI
I
VI
V
V
V
I
V
IV
V
V
VI
V
V
IV
IV
VI
I
VI
VI
V
V
IV
IV
VI
V
I
I
V
V
VI
VI
2.4
DD
= 3.3 V, V
CC
= 5 V; internal reference; differential encode input, unless otherwise noted.)
◊
Temp
Test
Level
AD9433BSQ-105
Min
Typ
Max
12
Guaranteed
0
+5
1
+3
0.25 +0.75
+1
0.5
+1.0
+1.3
–50
–125
±
80
2.5
100
2.6
50
2.0
4.0
3
4
750
5.0
1275
3
255
12.5
3.75
500
–0.5
2.0
6
3
2.0
0.8
50
50
V
DD
– 0.05
V
CC
+ 0.05
4.25
AD9433BSQ-125
Min
Typ
Max
12
Guaranteed
0
+5
1
+3
0.3 +0.75
+1
0.5 +1.0
+1.3
–50
–125
±
80
2.4
2.5
100
2.6
50
2.0
4.0
3
4
750
5.0
1350
3
270
16
3.75
500
–0.5
2.0
6
3
2.0
0.8
50
50
Unit
Bits
–5
–7
–0.75
–1
–1.0
–1.3
–5
–7
–0.75
–1
–1.0
–1.3
mV
% FS
LSB
LSB
LSB
LSB
ppm/ C
ppm/ C
ppm/ C
V
µA
µA
V
V
kΩ
pF
MHz
V
V
mW
mV/V
mA
mA
2
4
2
4
4.75
2.7
5.25
3.3
1425
285
14
4.75
2.7
5.25
3.3
1500
300
18
V
mV
V
CC
+ 0.05 V
4.25
V
kΩ
pF
V
V
µA
µA
V
V
V
DD
– 0.05
0.05
Two’s Complement or Offset Binary
0.05
NOTES
1
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2
SFDR disabled (SFDR = GND) for DNL and INL specifications.
3
Power dissipation measured with rated encode and a dc analog input (Outputs Static, I
VDD
= 0). I
VCC
and I
VDD
measured with 10.3 MHz analog input @ –0.5 dBFS.
Specifications subject to change without notice.
–2–
REV. 0
AD9433
AC SPECIFICATIONS
(V
Parameter
DYNAMIC PERFORMANCE*
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN
= 10.3 MHz
f
IN
= 49 MHz
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 250 MHz
Signal-to-Noise Ratio and Distortion (SINAD)
(With Harmonics)
f
IN
= 10.3 MHz
f
IN
= 49 MHz
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 250 MHz
Effective Number of Bits
f
IN
= 10.3 MHz
f
IN
= 49 MHz
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 250 MHz
2nd and 3rd Harmonic Distortion
f
IN
= 10.3 MHz
f
IN
= 49 MHz
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 250 MHz
Worst Other Harmonic or Spur
(Excluding Second and Third)
f
IN
= 10.3 MHz
f
IN
= 49 MHz
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 250 MHz
Two-Tone Intermod Distortion (IMD3)
f
IN1
= 49.3 MHz, f
IN2
= 50.3 MHz
f
IN1
= 150 MHz, f
IN2
= 151 MHz
DD
= 3.3 V, V
CC
= 5 V; differential encode input, unless otherwise noted.)
Temp
Test
Level
AD9433BSQ-105
Min
Typ
Max
AD9433BSQ-125
Min
Typ
Max
Unit
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
I
V
V
V
I
I
V
V
V
I
I
V
V
V
I
I
V
V
V
I
I
V
V
V
V
V
66.5
65.5
68.0
67.5
67.0
65.4
63.7
68.0
67.5
66.9
64.0
61.2
11.1
11.0
10.9
10.4
9.9
66.0
64.0
67.7
66.0
65.4
62.0
60.0
67.0
65.5
64.5
61.5
57.7
10.9
10.7
10.6
10.0
9.4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
66.0
64.0
65.0
63.5
–78
–73
–85
–80
–83
–72
–67
–92
–89
–87
–87
–85
–92
–80
–76
–72
–85
–76
–78
–67
–65
–90
–87
–85
–84
–76
–90
–76
–88
–82
–84
–82
25 C
25 C
*SNR/Harmonics
based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR active
(SFDR = +5 V). SNR/SINAD specified with SFDR disabled (SFDR = Ground).
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(V
Parameter
Encode Rate
Encode Pulsewidth High (t
EH
)
Encode Pulsewidth Low (t
EL
)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
1
Output Valid Time (t
V
)
2
Output Propagation Delay (t
PD
)
2
Output Rise Time (t
R
)
Output Fall Time (t
F
)
Out of Range Recovery Time
Transient Response Time
Latency
DD
= 3.3 V, V
CC
= 5 V; differential encode input, unless otherwise noted.)
Test
Level
IV
IV
IV
V
V
VI
VI
V
V
V
V
IV
AD9433BSQ-105
Min
Typ
Max
10
2.9
2.9
2.5
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
105
AD9433BSQ-125
Min
Typ
Max
10
2.4
2.4
2.5
5.5
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
125
Unit
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Temp
Full
Full
Full
25 C
25 C
Full
Full
Full
Full
25 C
25 C
Full
5.5
NOTES
1
Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit.
2
t
V
and t
PD
are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is
not to exceed an ac load of 10 pF or a dc current of 50
µA.
Rise and fall times measured from 10% to 90%.
Specifications subject to change without notice.
REV. 0
–3–
AD9433
ABSOLUTE MAXIMUM RATINGS*
THERMAL CHARCTERISTICS
Parameter
ELECTRICAL
V
DD
Voltage
V
CC
Voltage
Analog Input Voltage
Digital Input Voltage
Digital Output Current
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Maximum Junction
Temperature
Storage Temperature
Range (Ambient)
Min
–0.5
–0.5
–0.5
–0.5
Max
+6.0
+6.0
V
CC
+ 0.5
V
CC
+ 0.5
20
Unit
V
V
V
V
mA
Thermal Resitance
52-Lead PowerQuad
®
4 LQFP_ED
JA
= 25°C/W, Soldered Heat Sink, No Airflow
JA
= 33°C/W, Unsoldered Heat Sink, No Airflow
JC
= 2°C/W, Bottom of Package (Heat Sink)
Simulated typical performance for 4-layer JEDEC board, horizontal orientation.
EXPLANATION OF TEST LEVELS
Test Level
–40
+85
+150
C
C
C
I
II
–65
+125
*Stresses
greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
100% production tested.
100% production tested at 25 C and guaranteed by design
and characterization at specified temperatures.
III Sample Tested Only
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25 C and guaranteed by design
and characterization for industrial temperature range.
ORDERING GUIDE
Model
AD9433BSQ-105
AD9433BSQ-125
AD9433/PCB
Temperature Range
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
25°C
Package Description
52-Lead Plastic Thermally Enhanced Quad Flatpack
52-Lead Plastic Thermally Enhanced Quad Flatpack
Evaluation Board with AD9433BSQ-125
(Supports – 105 Evaluation)
Package Option
SQ-52
SQ-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9433 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PowerQuad is a registered trademark of AMkor Technology, Inc.
–4–
REV. 0
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AD9433BSQ-125 Related Products

AD9433BSQ-125 AD9433BSQZ-125 AD9433BSQ-105 AD9433BSQZ-105
Description 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, POWER, PLASTIC, LQFP-52
Is it lead-free? Contains lead Lead free Contains lead Lead free
Is it Rohs certified? incompatible conform to incompatible conform to
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
Parts packaging code QFP QFP QFP QFP
package instruction HLQFP, HLQFP, HLQFP, HLQFP,
Contacts 52 52 52 52
Reach Compliance Code unknown unknown unknown unknown
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 code S-PQFP-G52 S-PQFP-G52 S-PQFP-G52 S-PQFP-G52
JESD-609 code e0 e3 e0 e3
length 10 mm 10 mm 10 mm 10 mm
Maximum linear error (EL) 0.0317% 0.0317% 0.0317% 0.0317%
Humidity sensitivity level 3 3 3 3
Number of analog input channels 1 1 1 1
Number of digits 12 12 12 12
Number of functions 1 1 1 1
Number of terminals 52 52 52 52
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Output bit code OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY
Output format PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HLQFP HLQFP HLQFP HLQFP
Package shape SQUARE SQUARE SQUARE SQUARE
Package form FLATPACK, HEAT SINK/SLUG, LOW PROFILE FLATPACK, HEAT SINK/SLUG, LOW PROFILE FLATPACK, HEAT SINK/SLUG, LOW PROFILE FLATPACK, HEAT SINK/SLUG, LOW PROFILE
Peak Reflow Temperature (Celsius) 240 260 240 NOT APPLICABLE
Sampling rate 125 MHz 125 MHz 105 MHz 105 MHz
Sample and hold/Track and hold TRACK TRACK TRACK TRACK
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Nominal supply voltage 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
technology BICMOS BICMOS BICMOS BICMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD MATTE TIN TIN LEAD MATTE TIN
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature 30 40 30 NOT APPLICABLE
width 10 mm 10 mm 10 mm 10 mm

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STM32F769I-DISCO Review (2) STM32F769I-DISCO Official Data Collection
[color=#ff0000][b]STM32F769I-DISCO official introduction page:[/b][/color][url=http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tool...
dql2016 stm32/stm8
Hope to get a chance to use this FPGA
I don't know how this FPGA will perform......
flander_cx FPGA/CPLD
Calculation of mixed ratios of multiple colors for LCD
[i=s]This post was last edited by shipeng on 2020-5-9 15:24[/i]I suddenly had an idea: Can the LCD font be scaled down according to the required proportion, so that all font sizes share a set of dot m...
shipeng MCU
Problems configuring ADC in DAVE
[color=#333333][font=arial, Simsun, 宋体][size=12px] [/size][/font][/color] [color=#333333][font=arial, Simsun, 宋体][size=12px] The division frequency of the analog signal clock and the digital signal cl...
1157421908 TI Technology Forum
Help, make FPGA board
I need to make a board to realize baseband modulation. The chip I initially selected is EP2C8Q208C8. The input is from RS232 and the output is connected to a D/A. I found the schematic diagram of the ...
budie FPGA/CPLD
When compiling rt-thread in IAR environment, the .icf file writing precautions
I've been working on the RT-Thread system recently. Since my MCU is LPC1778 and I prefer to use the IAR environment, I checked the source code for the IAR project for LPC1768. I copied the IAR project...
zhouguoping Real-time operating system RTOS
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