THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
ADVANCE INFORMATION
DS3647-1·2
SP8690
200MHz410/11
4
SP8691
200MHz48/9
4
The SP8690 and SP8691 are low power ECL variable
modulus dividers, with both ECL10K and TTL/CMOS compatible
outputs. They divide by the lower division ratio when either of
the ECL control inputs, PE1 or PE2, is in the high state and by
the higher ratio when both are low (or open circuit).
CLOCK INPUT
CONTROL INPUTS
1
2
3
4
5
6
7
8
16
15
14
CLOCK INPUT
NC
NC
NC
V
EE
TTL/CMOS OUTPUT
NC
ECL OUTPUT
PE1
PE2
NC
V
CC
NC
NC
FEATURES
s
ECL and TTL/CMOS Compatible Outputs
s
AC-Coupled Input
s
Control Inputs ECL Compatible
QUICK REFERENCE DATA
SP8690
SP8691
13
12
11
10
ECL OUTPUT
9
s
Supply Voltage:
25·2V60·25V
(ECL), 5V60·25V (TTL)
s
Power Consumption: 70mW (Typ.)
s
Temperature Range:
255°C
to
1125°C
(A Grade)
230°C
to
170°C
(B Grade)
DG16
Fig. 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage, |V
CC
2V
EE
|
ECL output current
Storage temperature range
Max. junction temperature
TTL output voltage
Input voltage
Max. open collector current
8V
10mA
265°C
to
1150°C
1175°C
112V
2·5V p-p
15mA
ORDERING INFORMATION
SP8690 A DG
SP8690 B DG
SP8691 A DG
5962-87678 (SMD)
(SP8690)
V
CC
5
D1
PE1
PE2
CLOCK INPUT
CLOCK INPUT
2
3
Q1
D2
Q2
D3
Q3
D4
Q4
8
ECL OUTPUT
Q4
1
16
12
V
EE
9
ECL OUTPUT
11
TTL/CMOS
OUTPUT
Fig. 2 Functional diagram (SP8690)
SP8690/SP8691
V
CC
5
PE1
PE2
2
3
D1
Q1
D2
Q2
D3
Q3
D4
Q4
8
ECL OUTPUT
Q2
CLOCK INPUT
CLOCK INPUT
1
16
12
V
EE
Q4
9
ECL OUTPUT
11
TTL/CMOS
OUTPUT
Fig. 3 Functional diagram (SP8691)
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
ECL OPERATION
Supply voltage, V
CC
= 0V, V
EE
=
25·2V 6
0·25V
Temperature, T
AMB
=
255°C
to
1125°C
(A Grade),
230°C
to
170°C
(B Grade)
Characteristic
Symbol
f
MAX
f
MIN
I
EE
V
OH
V
OL
V
INH
V
INL
t
p
t
s
t
r
Value
Min.
200
40
21
20·7
21·5
21·62
9
3
8
Max.
MHz
MHz
mA
V
V
V
V
ns
ns
ns
Input = 400-800mV p-p
Input = 400-800mV p-p
V
EE
=
25·0V
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
5
5
5
Units
Conditions
Notes
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
ECL output high voltage
ECL output low voltage
PE input high voltage
PE input low voltage
Clock to ECL output delay
Set-up time
Release time
20·85
21·8
20·93
6
3, 6
4, 6
TTL OPERATION
Supply voltage, V
CC
= 5V
6
0·25V, V
EE
= 0V
Temperature, T
AMB
=
255°C
to
1125°C
(A Grade),
230°C
to
170°C
(B Grade)
Characteristic
Symbol
f
MAX
f
MIN
I
EE
V
OL
V
OH
t
PLH
t
PHL
t
s
t
r
Value
Min.
200
40
21
0·5
3·75
32
18
3
8
Max.
MHz
MHz
mA
V
V
ns
ns
ns
ns
Input = 400-800mV p-p
Input = 400-800mV p-p
V
CC
= 5·0V
V
CC
= 5V, R
L
= 560Ω
R
L
= 560Ω
R
L
= 560Ω
R
L
= 560Ω
5
5
5
5, 7
5, 7
6
6
3, 6
4, 6
Units
Conditions
Notes
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
TTL output low voltage
TTL output high voltage
Clock to TTL output high delay,1ve going
Clock to TTL output low delay,2ve going
Set-up time
Release time
NOTES
1. The temperature coefficients of V
OH
=
11·63mV/°C,
V
OL
=
10·94mV/°C
and of V
IN
=
11·22mV/°C.
2. The test configuration for dynamic testing is shown in Fig.8
3. The set-up time t
s
is defined as the minimum time that can elapse between L→H transition of control input and the next L→H clock pulse transition
to ensure that division by the lower modulus is obtained.
4. The release time t
r
is defined as the minimum time that can elapse between H→L transition of control input and the next L→H clock pulse transition
to ensure that division by the higher modulus is obtained.
5. SP8690/1B tested at 25°C only.
6. Guaranteed but not tested.
7. The open collector output is not recommended for use at output frequencies above 15MHz. C
LOAD
≤
5pF.
2
SP8690/SP8691
CLOCK INPUT
TRUTH TABLE FOR
CONTROL INPUTS
t
r
t
s
PE1
L
H
L
H
PE2
L
L
H
H
Division ratio
11
10
10
10
PE INPUTS
6
ECL AND TTL
OUTPUTS
5
5
5
Fig. 4 Timing diagram, SP8690
TRUTH TABLE FOR
CONTROL INPUTS
t
r
PE INPUTS
CLOCK INPUT
t
s
PE1
L
H
L
H
PE2
L
L
H
H
Division ratio
9
8
8
8
5
ECL AND TTL
OUTPUTS
4
4
4
Fig. 5 Timing diagram, SP8691
1200
INPUT AMPLITUDE (mV p-p)
1000
800
600
400
255°C
1125°C
GUARANTEED
*
OPERATING
WINDOW
*
Tested as specified
in table of Electrical
Characteristics
200
0
0
50
100
150
INPUT FREQUENCY (MHz)
200
250
Fig. 6 Typical input characteristics, SP8690/1
j1
j
0.5
j2
j
0.2
j5
0
0.2
0.5
1
2
5
50
100
2
j
0.2
150
200
2
j
0.5
2
j
1
2
j
2
2
j
5
Fig. 7 Typical input impedance. Test conditions: Supply Voltage = 5.0V,
Ambient Temperature = 25°C. Frequencies in MHz, impedances normalised to 50Ω.
3
SP8690/SP8691
V
CC
560
2·4k
10n
INPUT FROM
GENERATOR
33
INPUT
MONITOR
33
16
1
10n
20
2
5
11
Q4
9
8
450
450
0.1µ
0.1µ
0.1µ
DUT
Q4
3
12
OUTPUTS TO
SAMPLING
SCOPE
V
EE
Fig. 8 Test circuit for dynamic measurements
V
CC
1·5k
TTL
CONTROL INPUT
(SEE TRUTH TABLES,
FIGS. 4 AND 5)
10n
CLOCK
INPUT
5
1
10k
10k
3·6k
O/C
2
3
11
TTL
OUTPUT
560
8
16
DIVIDE BY
10/11 (SP8690)
8/9 (SP8691)
9
91
ECL10K
OUTPUT
3k
3k
10n
68k
BIAS
3k
3k
8
V
EE
Fig. 9 Typical application showing interfacing.
OPERATING NOTES
1. The clock inputs can be single or differentially driven. The
clock input is biased internally and is coupled to the signal
source with a suitable capacitor. The input signal path is
completed by an input reference decoupling capacitor which
is connected to ground.
2. In the absence of a signal the device will self-oscillate. If
this is undesirable, it may be prevented by connecting a
68kΩ resistor from the input to V
EE
i.e., from pin 1 or pin 16
to pin 12. This reduces the input sensitiviy by approximately
100mV.
3. The circuit will operate down to DC but slew rate must be
better than 100V/µs.
4. The Q
4
and Q
4
outputs are compatible with ECLII but can
be interfaced to ECL10K as shown in Fig. 9.
5. The PE inputs are ECLIII/10K compatible and include
internal 10kΩ pulldown resistors. Unused inputs can therefore
be left open circuit.
6. The input impedance of the SP8690/1 varies as a function
of frequency. See Fig. 7.
7. The TTL/CMOS output is a free collector and the high
state output voltage will depend on the supply that the
collector load is taken to. This should not exceed 12V.
8. The rise/fall time of the open collector output waveform is
directly proportional to load capacitance and load resistor
value. Therefore, load capacitance should be minimised
and the load resistor kept to a minimum consistent with
system power requirements. In the test configuration of Fig.
8 the output rise time is approximately 10ns and the fall time
4
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